Design, development and testing of a 16-bit reduced instruction set computer architecture based processor

The design of efficient processors with customized functionality is the need for low-power embedded systems. A 16-bit processor is suitable for such systems compared to a 32-bit processor due to low power consumption. In this paper, we proposed a design of a 16-bit processor based on reduced instruc...

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Vydáno v:	Sadhana (Bangalore) Ročník 48; číslo 4; s. 244
Hlavní autoři:	Jain, Manan, Kanzariya, Het, Joshi, Neel, Masharu, Yesha, Gajjar, Sachin, Shah, Dhaval
Médium:	Journal Article
Jazyk:	angličtina
Vydáno:	New Delhi Springer India 04.11.2023 Springer Nature B.V
Témata:	Computer architecture Control algorithms Design Embedded systems Engineering Hardware description languages Instruction sets (computers) Microprocessors Power consumption Power management RISC Verification RISC multi-cycle datapath processor architecture Instruction set architecture (ISA)
ISSN:	0973-7677, 0256-2499, 0973-7677
On-line přístup:	Získat plný text
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