Design, development and testing of a 16-bit reduced instruction set computer architecture based processor

The design of efficient processors with customized functionality is the need for low-power embedded systems. A 16-bit processor is suitable for such systems compared to a 32-bit processor due to low power consumption. In this paper, we proposed a design of a 16-bit processor based on reduced instruc...

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Vydáno v:Sadhana (Bangalore) Ročník 48; číslo 4; s. 244
Hlavní autoři: Jain, Manan, Kanzariya, Het, Joshi, Neel, Masharu, Yesha, Gajjar, Sachin, Shah, Dhaval
Médium: Journal Article
Jazyk:angličtina
Vydáno: New Delhi Springer India 04.11.2023
Springer Nature B.V
Témata:
Computer architecture
Control algorithms
Design
Embedded systems
Engineering
Hardware description languages
Instruction sets (computers)
Microprocessors
Power consumption
Power management
RISC
Verification
RISC
multi-cycle datapath
processor architecture
Instruction set architecture (ISA)
ISSN:0973-7677, 0256-2499, 0973-7677
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Shrnutí:The design of efficient processors with customized functionality is the need for low-power embedded systems. A 16-bit processor is suitable for such systems compared to a 32-bit processor due to low power consumption. In this paper, we proposed a design of a 16-bit processor based on reduced instruction set computer (RISC) architecture using a multicycle data path. The design, development, and verification were carried-out using Xilinx Vivado, Xilinx Power Estimator, and Modelsim tools. The design of the processor is implemented on Spartan 7 (XC7S6- 2CPGA196C) FPGA board using Verilog hardware description language (HDL). The verification of the designed processor is performed through the execution of a set of instructions. The proposed RISC processor design utilizes about half of the computing resources compared to traditional 16-bit processors and hence achieves significantly lesser power consumption.
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ISSN:0973-7677
0256-2499
0973-7677
DOI:10.1007/s12046-023-02304-y