Jain, M., Kanzariya, H., Joshi, N., Masharu, Y., Gajjar, S., & Shah, D. (2023). Design, development and testing of a 16-bit reduced instruction set computer architecture based processor. Sadhana (Bangalore), 48(4), 244. https://doi.org/10.1007/s12046-023-02304-y
Citace podle Chicago (17th ed.)Jain, Manan, Het Kanzariya, Neel Joshi, Yesha Masharu, Sachin Gajjar, a Dhaval Shah. "Design, Development and Testing of a 16-bit Reduced Instruction Set Computer Architecture Based Processor." Sadhana (Bangalore) 48, no. 4 (2023): 244. https://doi.org/10.1007/s12046-023-02304-y.
Citace podle MLA (9th ed.)Jain, Manan, et al. "Design, Development and Testing of a 16-bit Reduced Instruction Set Computer Architecture Based Processor." Sadhana (Bangalore), vol. 48, no. 4, 2023, p. 244, https://doi.org/10.1007/s12046-023-02304-y.