Design and Performance Evaluation of a Novel High-Speed Hardware Architecture for Keccak Crypto Coprocessor

The Keccak algorithm plays a significant role in ensuring the security and confidentiality of data in modern information systems. However, it involves computational complexities that can hinder high-performance applications. This paper proposes a novel high-performance hardware architecture for the...

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Bibliographic Details
Published in:	International journal of parallel programming Vol. 52; no. 5-6; pp. 367 - 379
Main Author:	Sanlı, Mustafa
Format:	Journal Article
Language:	English
Published:	New York Springer US 01.12.2024 Springer Nature B.V
Subjects:	Algorithms Computer architecture Computer Science Cryptography Data processing Field programmable gate arrays Hardware High performance systems Information systems Parallel processing Performance evaluation Pipelining (computers) Processor Architectures Software Engineering/Programming and Operating Systems Theory of Computation Hash function FPGA Embedded system Keccak
ISSN:	0885-7458, 1573-7640
Online Access:	Get full text
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