Design and Performance Evaluation of a Novel High-Speed Hardware Architecture for Keccak Crypto Coprocessor

The Keccak algorithm plays a significant role in ensuring the security and confidentiality of data in modern information systems. However, it involves computational complexities that can hinder high-performance applications. This paper proposes a novel high-performance hardware architecture for the...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Veröffentlicht in:	International journal of parallel programming Jg. 52; H. 5-6; S. 367 - 379
1. Verfasser:	Sanlı, Mustafa
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	New York Springer US 01.12.2024 Springer Nature B.V
Schlagworte:	Algorithms Computer architecture Computer Science Cryptography Data processing Field programmable gate arrays Hardware High performance systems Information systems Parallel processing Performance evaluation Pipelining (computers) Processor Architectures Software Engineering/Programming and Operating Systems Theory of Computation Hash function FPGA Embedded system Keccak
ISSN:	0885-7458, 1573-7640
Online-Zugang:	Volltext
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

Schreiben Sie den ersten Kommentar!