Analysis of Degradation Mechanisms of Gate Dielectrics Based on SiO2 in MOS Transistors

The current mathematical models of gate dielectric degradation are used to determine the value of a device’s operating time to failure depending on its internal properties and operating conditions. These models significantly reduce the time and material costs for testing and processing large amounts...

Full description

Saved in:
Bibliographic Details
Published in:Semiconductors (Woodbury, N.Y.) Vol. 55; no. 13; pp. 1045 - 1048
Main Authors: Eliseeva, D. A., Safonov, S. O.
Format: Journal Article
Language:English
Published: Moscow Pleiades Publishing 01.12.2021
Springer Nature B.V
Subjects:
Degradation
Dielectrics
Electric fields
Elements of Integrated Electronics
Magnetic Materials
Magnetism
Mathematical models
MOS devices
Physics
Physics and Astronomy
Semiconductor devices
Silicon dioxide
Thickness
Transistors
time-dependent dielectric breakdown
MOS transistor
gate dielectric
reliability
ISSN:1063-7826, 1090-6479
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:The current mathematical models of gate dielectric degradation are used to determine the value of a device’s operating time to failure depending on its internal properties and operating conditions. These models significantly reduce the time and material costs for testing and processing large amounts of experimental data. Here, the gate dielectrics based on SiO 2 in n - and p -channel MOS transistors are investigated. It is found that, when exposed to an electric field, the gate dielectric with the thickness of 5.3 nm most likely degrades according to the thermochemical model ( E -model), and the one with a thickness of 7 nm, according to the anode hole injection model (1/ E -model). The coefficients are calculated, and the analysis of mathematical models is carried out, which makes it possible to determine the lifetime of gate dielectrics based on SiO 2 7 nm thick in n - and p -channel MOS transistors and those that are 5.3 nm thick in n -channel MOS transistors at different values of their area, operating voltage, and temperature. This study can serve as a method for monitoring and determining the quality of the gate dielectrics of the manufactured MOS transistors.
Bibliography:ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 14
ISSN:1063-7826
1090-6479
DOI:10.1134/S1063782621130054