Modified stable Euler-number algorithm implementation for real-time image binarization

The stable Euler-number-based image binarization has been shown to give excellent visual results for images containing high amount of image noise. Being computationally expensive, its applications are limited mostly to general-purpose processors and in application specific integrated circuits. In th...

Celý popis

Uloženo v:
Podrobná bibliografie
Vydáno v:Journal of real-time image processing Ročník 9; číslo 1; s. 31 - 45
Hlavní autoři: Abbasi, Naeem, Athow, Jacques, Amer, Aishy
Médium: Journal Article
Jazyk:angličtina
Vydáno: Berlin/Heidelberg Springer Berlin Heidelberg 01.03.2014
Springer Nature B.V
Témata:
Algorithms
Application specific integrated circuits
Computer architecture
Computer Graphics
Computer Science
Field programmable gate arrays
Hardware
Image Processing and Computer Vision
Input output
Multimedia Information Systems
Pattern Recognition
Real time
Signal,Image and Speech Processing
Software
Special Issue
Stable Euler Number
Pipelined architecture
FPGA
Image binarization
Real-time
ISSN:1861-8200, 1861-8219
On-line přístup:Získat plný text
Tagy: Přidat tag
Žádné tagy, Buďte první, kdo vytvoří štítek k tomuto záznamu!
Popis
Shrnutí:The stable Euler-number-based image binarization has been shown to give excellent visual results for images containing high amount of image noise. Being computationally expensive, its applications are limited mostly to general-purpose processors and in application specific integrated circuits. In this paper a modified stable Euler-number-based algorithm for image binarization is proposed and its real-time hardware implementation in a Field Programmable Gate Array with a pipelined architecture is presented. The proposed modifications to the algorithm facilitate hardware implementation. The end result is a design that out-performs known software implementations. The amount of noisy pixels introduced during the binarization process is also minimized. Despite the stable Euler-number-based image binarization being computationally expensive, our simulations show that the proposed architecture gives accurate results and this in real time and without consuming all chip resources.
Bibliografie:ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 14
ISSN:1861-8200
1861-8219
DOI:10.1007/s11554-012-0296-z