Modified stable Euler-number algorithm implementation for real-time image binarization

The stable Euler-number-based image binarization has been shown to give excellent visual results for images containing high amount of image noise. Being computationally expensive, its applications are limited mostly to general-purpose processors and in application specific integrated circuits. In th...

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Veröffentlicht in:Journal of real-time image processing Jg. 9; H. 1; S. 31 - 45
Hauptverfasser: Abbasi, Naeem, Athow, Jacques, Amer, Aishy
Format: Journal Article
Sprache:Englisch
Veröffentlicht: Berlin/Heidelberg Springer Berlin Heidelberg 01.03.2014
Springer Nature B.V
Schlagworte:
Algorithms
Application specific integrated circuits
Computer architecture
Computer Graphics
Computer Science
Field programmable gate arrays
Hardware
Image Processing and Computer Vision
Input output
Multimedia Information Systems
Pattern Recognition
Real time
Signal,Image and Speech Processing
Software
Special Issue
Stable Euler Number
Pipelined architecture
FPGA
Image binarization
Real-time
ISSN:1861-8200, 1861-8219
Online-Zugang:Volltext
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Zusammenfassung:The stable Euler-number-based image binarization has been shown to give excellent visual results for images containing high amount of image noise. Being computationally expensive, its applications are limited mostly to general-purpose processors and in application specific integrated circuits. In this paper a modified stable Euler-number-based algorithm for image binarization is proposed and its real-time hardware implementation in a Field Programmable Gate Array with a pipelined architecture is presented. The proposed modifications to the algorithm facilitate hardware implementation. The end result is a design that out-performs known software implementations. The amount of noisy pixels introduced during the binarization process is also minimized. Despite the stable Euler-number-based image binarization being computationally expensive, our simulations show that the proposed architecture gives accurate results and this in real time and without consuming all chip resources.
Bibliographie:ObjectType-Article-1
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ISSN:1861-8200
1861-8219
DOI:10.1007/s11554-012-0296-z