Improved usability and performance of SMT solvers for debugging specifications
It is now common to construct an extended static checker or software verification system using an SMT theorem prover as the underlying logical verifier. SMT provers have improved significantly in performance over the last several years. However, their usability as a component of software checking an...
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| Vydané v: | International journal on software tools for technology transfer Ročník 12; číslo 6; s. 467 - 481 |
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| Hlavný autor: | |
| Médium: | Journal Article Konferenčný príspevok.. |
| Jazyk: | English |
| Vydavateľské údaje: |
Berlin/Heidelberg
Springer-Verlag
01.11.2010
Springer |
| Predmet: | |
| ISSN: | 1433-2779, 1433-2787 |
| On-line prístup: | Získať plný text |
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| Shrnutí: | It is now common to construct an extended static checker or software verification system using an SMT theorem prover as the underlying logical verifier. SMT provers have improved significantly in performance over the last several years. However, their usability as a component of software checking and verification systems still has gaps. This paper describes investigations in two areas: the reporting of counterexample information and the testing of vacuity, both of which are important to realistic use of such tools for typical software development. The use of solvers in verification is more effective if the solvers support minimal unsatisfiable cores and incremental construction, evolution and querying of satisfying assignments; current solvers only partially support these capabilities. |
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| Bibliografia: | ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 23 |
| ISSN: | 1433-2779 1433-2787 |
| DOI: | 10.1007/s10009-010-0138-x |