An Efficient Optimization and Secured Triple Data Encryption Standard Using Enhanced Key Scheduling Algorithm
As a result of advancement in technology, the transfer rate of digital data through cryptographic embedded devices such as smart cards is increasing rapidly and these devices are vulnerable to attacks. Cryptography provides various algorithms to secure the data. Triple Data Encryption Standard (Trip...
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| Published in: | Procedia computer science Vol. 171; pp. 1054 - 1063 |
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| Main Authors: | , , , |
| Format: | Journal Article |
| Language: | English |
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Elsevier B.V
2020
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| ISSN: | 1877-0509, 1877-0509 |
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| Abstract | As a result of advancement in technology, the transfer rate of digital data through cryptographic embedded devices such as smart cards is increasing rapidly and these devices are vulnerable to attacks. Cryptography provides various algorithms to secure the data. Triple Data Encryption Standard (Triple-DES) algorithm [1] is one such and uses the Data Encryption Standard (DES) block thrice this reinforces the key size to 192 bits. The reliability of data can be made progressive by procuring the keys. In Triple-DES, the key generation does not undergo encryption, making the job of the cryptanalyst easy. A strategy must be followed to make the keys more reliable and avoid the glitches in the power traces to make it more strenuous for them. To satisfy the above requirement FORTIS algorithm has been proposed for generation of sub-keys and investigates the strength of the algorithm against side-channel power attacks using ChipWhisperer®-Lite and Artix FPGA as target board. The number of glitches that represent the leakage power are approximately reduced by 53.3% and from the power traces of key schedule algorithm it is seen that all the instructions being performed are similar, so it becomes difficult to identify which operation is being performed and the probability of guessing entropy has been reduced in 86.6% of the cases. |
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| AbstractList | As a result of advancement in technology, the transfer rate of digital data through cryptographic embedded devices such as smart cards is increasing rapidly and these devices are vulnerable to attacks. Cryptography provides various algorithms to secure the data. Triple Data Encryption Standard (Triple-DES) algorithm [1] is one such and uses the Data Encryption Standard (DES) block thrice this reinforces the key size to 192 bits. The reliability of data can be made progressive by procuring the keys. In Triple-DES, the key generation does not undergo encryption, making the job of the cryptanalyst easy. A strategy must be followed to make the keys more reliable and avoid the glitches in the power traces to make it more strenuous for them. To satisfy the above requirement FORTIS algorithm has been proposed for generation of sub-keys and investigates the strength of the algorithm against side-channel power attacks using ChipWhisperer®-Lite and Artix FPGA as target board. The number of glitches that represent the leakage power are approximately reduced by 53.3% and from the power traces of key schedule algorithm it is seen that all the instructions being performed are similar, so it becomes difficult to identify which operation is being performed and the probability of guessing entropy has been reduced in 86.6% of the cases. |
| Author | Roshan, R Sai Vuppala, Akshitha Nawaz, Shaik Ravindra, JVR |
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| Cites_doi | 10.1109/AIAIM.2019.8632786 10.1049/ip-cds:20030574 10.1109/ISSCS.2017.8034875 10.1109/ICCECE.2017.8526233 10.1109/IWAIT.2018.8369682 10.1109/DCABES.2012.42 10.1109/MENACOMM.2018.8371019 10.1109/ICSESS.2014.6933619 10.1109/ICDMA.2012.29 10.1109/FPL.2006.311315 |
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| Keywords | DES VLSI Hardware security Encryption Standard |
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| References_xml | – reference: Harshali. D. Zodpe, Prakash W.Wani, Rakesh R. Mehta (2012) "Design and implementation of algorithm for DES cryptanalysis," in International Conference on Hybrid Intelligent Systems. – reference: Saptarshi Mitra, Bappaditya Jana, Jayanta Poray (2017) "Implementation of novel security techniques using Triple-DES in cashless transactions," in International Conference on Computer, Electrical and Communication Engineering (ICCECE). – reference: H. Rehman, S. Jamshed, Absar ul Haq (2002) "Why triple DES with 128-bit key and not Rijandel should be AES," in IEEE Students Conference. – reference: Tom T. Karygiannis, L Owens Reading (2002) "Wireless Network Security: 802.11, Bluetooth and Handheld Devices. " – reference: Linxian Zhi (2012) "Research of Image Encryption Algorithm Based on S-DES," in IEEE International Conference on Computer Science and Electronics Engineering. – reference: M. Mc Loone, J.V. McCanny (2003) "High-performance FPGA implementation of DES using a novel method for implementing the Key schedule," in IEEE Proceedings – Circuits, Devices and Systems. – reference: Reatrey Pich, Sorawat Chivapreecha, Jaruwit Prabnasak (2018) "A single, triple chaotic cryptography using chaos in digital filter and its own comparison to DES and triple DES," in International Workshop on Advanced Image Technology (IWAIT). – reference: Li Wang, Guangling Jiang (2019) "The Design of 3-DES Encryption System Using Optimizing Keys", in China-Qatar International Workshop on Artificial Intelligence and Applications to Intelligent Manufacturing (AIAIM). – reference: Mohamad Noura, Hassan N.Noura, Ali chehab, Mohammad M. Mansour, Raphel Couturier (2018) "S-DES: An efficient and secure DES variant." in Middle East and North Africa COMMunications Conference (MENACOMM). – reference: Luminita Scripcariu, Petre-Daniel Matasaru (2017) "Extended DES algorithm to Galois Fields," in International Symposium on Signals, Circuits and Systems(ISSCS). – reference: Zhou Yingbing, Li Yongzhen (2014) "The design and implementation of a symmetric encryption algorithm based on DES," in IEEE international conference on software engineering and Service Science. – reference: John Kelsey, Bruce Schneier, David Wagner (2001) "Key-Schedule Cryptanalysis of IDEA, G-DES, GOST, SAFER, and Triple-DES," in Annual International Cryptology Conference. – reference: I. Raja Sekhar Reddy, G. Murali (2017) "A novel triple DES to enhance E-governance security," in International Conference on Energy, Communication, Data Analytics and Soft Computing (ICECDS). – reference: Mohammed M. Alani (2010) "DES96- improved DES security," in International Multi- Conference on Systems, Signals and Devices. – reference: P. Hamalainen, M. Hannikainen, T. Hamalainen, J.Saarinen (2001) "Configurable hardware implementation of triple-DES encryption algorithm for wireless local area network," in IEEE International Conference on Acoustics, Speech, and Signal Processing. – reference: Jian Zhang, Xuling Jin (2012) "Encryption System Design Based on DES and SHA-1," in International Symposium on Distributed Computing and Applications to Business, Engineering and Science. – reference: Hsiu-Pang Yeh, Yue-Shan Chang, Chia-Feng Lin, Shyan-Ming Yuan (2011) "Accelerating 3-DES Performance Using GPU," in International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery. – reference: P. Kitsos, S. Goudevenos, and O. Koufopavlou (2003) "VLSI implementations of the triple-DES block cipher", in International Conference on Electronics Circuits and Systems (ICECS). – year: 2016 ident: bib0008 publication-title: Digital watermarking using spatial domain and triple DES – reference: F.-x. Standaert, G. Rouvroy, J.-j. Quisquater (2006) "FPGA Implementations of the DES and Triple-DES Masked Against Power Analysis Attacks", in International Conference on Field Programmable logic and Applications. – reference: L Jie, Lv Yuxiang, Sun Huafang, Shan Weiwei (2012) "A Power Analysis Resistant DES Cryptographic Algorithm and its Hardware Design," in IEEE International Conference on Digital Manufacturing and Automation. – ident: 10.1016/j.procs.2020.04.113_bib0004 doi: 10.1109/AIAIM.2019.8632786 – ident: 10.1016/j.procs.2020.04.113_bib00016 doi: 10.1049/ip-cds:20030574 – ident: 10.1016/j.procs.2020.04.113_bib00011 – ident: 10.1016/j.procs.2020.04.113_bib00014 – year: 2016 ident: 10.1016/j.procs.2020.04.113_bib0008 – ident: 10.1016/j.procs.2020.04.113_bib0005 doi: 10.1109/ISSCS.2017.8034875 – ident: 10.1016/j.procs.2020.04.113_bib00020 – ident: 10.1016/j.procs.2020.04.113_bib0006 doi: 10.1109/ICCECE.2017.8526233 – ident: 10.1016/j.procs.2020.04.113_bib00019 doi: 10.1109/IWAIT.2018.8369682 – ident: 10.1016/j.procs.2020.04.113_bib00010 doi: 10.1109/DCABES.2012.42 – ident: 10.1016/j.procs.2020.04.113_bib00013 doi: 10.1109/MENACOMM.2018.8371019 – ident: 10.1016/j.procs.2020.04.113_bib0009 – ident: 10.1016/j.procs.2020.04.113_bib00017 doi: 10.1109/ICSESS.2014.6933619 – ident: 10.1016/j.procs.2020.04.113_bib00021 – ident: 10.1016/j.procs.2020.04.113_bib00015 doi: 10.1109/ICDMA.2012.29 – ident: 10.1016/j.procs.2020.04.113_bib0003 – ident: 10.1016/j.procs.2020.04.113_bib00018 – ident: 10.1016/j.procs.2020.04.113_bib00012 doi: 10.1109/FPL.2006.311315 – ident: 10.1016/j.procs.2020.04.113_bib0001 – ident: 10.1016/j.procs.2020.04.113_bib0002 – ident: 10.1016/j.procs.2020.04.113_bib0007 |
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| Title | An Efficient Optimization and Secured Triple Data Encryption Standard Using Enhanced Key Scheduling Algorithm |
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