Hardware Architecture Design of Block-Matching and 3D-Filtering Denoising Algorithm

Block-matching and 3D-filtering（BM3D） is a state of the art denoising algorithm for image/video,which takes full advantages of the spatial correlation and the temporal correlation of the video. The algorithm performance comes at the price of more similar blocks finding and filtering which bring high...

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Bibliographic Details
Published in:Shanghai jiao tong da xue xue bao Vol. 21; no. 2; pp. 173 - 183
Main Author: 张昊 刘文江 王若琳 刘涛 戎蒙恬
Format: Journal Article
Language:English
Published: Shanghai Shanghai Jiaotong University Press 01.04.2016
Subjects:
Algorithms
Architecture
Computation
Computer Science
Correlation
Design engineering
Electrical Engineering
Engineering
Life Sciences
Materials Science
Noise reduction
Real time
Searching
3Dfiltering
A
implementation
block-matching and 3D-filtering (BM3D) denoising algorithm
aggregation
TN 47
block-matching
ISSN:1007-1172, 1995-8188
Online Access:Get full text
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Summary:Block-matching and 3D-filtering（BM3D） is a state of the art denoising algorithm for image/video,which takes full advantages of the spatial correlation and the temporal correlation of the video. The algorithm performance comes at the price of more similar blocks finding and filtering which bring high computation and memory access. Area, memory bandwidth and computation are the major bottlenecks to design a feasible architecture because of large frame size and search range. In this paper, we introduce a novel structure to increase data reuse rate and reduce the internal static-random-access-memory（SRAM） memory. Our target is to design a phase alternating line（PAL） or real-time processing chip of BM3 D. We propose an application specific integrated circuit（ASIC） architecture of BM3 D for a 720 × 576 BT656 PAL format. The feature of the chip is with 100 MHz system frequency and a 166-MHz 32-bit double data rate（DDR）. When noise is σ = 25, we successfully realize real-time denoising and achieve about 10 d B peak signal to noise ratio（PSNR） advance just by one iteration of the BM3 D algorithm.
Bibliography:31-1943/U
Block-matching and 3D-filtering（BM3D） is a state of the art denoising algorithm for image/video,which takes full advantages of the spatial correlation and the temporal correlation of the video. The algorithm performance comes at the price of more similar blocks finding and filtering which bring high computation and memory access. Area, memory bandwidth and computation are the major bottlenecks to design a feasible architecture because of large frame size and search range. In this paper, we introduce a novel structure to increase data reuse rate and reduce the internal static-random-access-memory（SRAM） memory. Our target is to design a phase alternating line（PAL） or real-time processing chip of BM3 D. We propose an application specific integrated circuit（ASIC） architecture of BM3 D for a 720 × 576 BT656 PAL format. The feature of the chip is with 100 MHz system frequency and a 166-MHz 32-bit double data rate（DDR）. When noise is σ = 25, we successfully realize real-time denoising and achieve about 10 d B peak signal to noise ratio（PSNR） advance just by one iteration of the BM3 D algorithm.
ZHANG Hao, LIU Wenjiang, WANG Ruolin, LIU Tao, RONG Mengtian（Key Laboratory of Ministry of Education of Design and Electromagnetic Compatibility of High-Speed Electronic Systems, Shanghai Jiaotong University, Shanghai 200240, China）
block-matching and 3D-filtering（BM3D） denoising algorithm implementation block-matching 3D-filtering aggregation
ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 23
ISSN:1007-1172
1995-8188
DOI:10.1007/s12204-016-1709-0