Hardware accelerated range Doppler algorithm for SAR data processing using Zynq processor

Purpose Synthetic aperture radar (SAR) imaging is the most computational intensive algorithm and this makes its implementation challenging for real-time application. This paper aims to present the chirp-scaling algorithm (CSA) for real-time SAR applications, using advanced field programmable gate ar...

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Veröffentlicht in:Circuit world Jg. 47; H. 2; S. 184 - 193
Hauptverfasser: Mewada, Hiren K, Chaudhari, Jitendra, Patel, Amit V, Mahant, Keyur, Vala, Alpesh
Format: Journal Article
Sprache:Englisch
Veröffentlicht: Bradford Emerald Publishing Limited 08.06.2021
Emerald Group Publishing Limited
Schlagworte:
Acceleration
Algorithms
Antennas
Chirp signals
Data processing
Digital signal processors
Fast Fourier transformations
Field programmable gate arrays
Fourier transforms
Hardware
Intellectual property
Microprocessors
Multiplication
Neon
Optimization
Radar
Radar imaging
Real time
Signal processing
Software
Surveillance
Synthetic aperture radar
FPGA
Chirp-scaling algorithm
Synthetic aperture radar
ISSN:0305-6120, 1758-602X
Online-Zugang:Volltext
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Zusammenfassung:Purpose Synthetic aperture radar (SAR) imaging is the most computational intensive algorithm and this makes its implementation challenging for real-time application. This paper aims to present the chirp-scaling algorithm (CSA) for real-time SAR applications, using advanced field programmable gate array (FPGA) processor. Design/methodology/approach A chirp signal is generated and compressed using range Doppler algorithm in MATAB for validation. Fast Fourier transform (FFT) and multiplication operations with complex data types are the major units requiring heavy computation. Therefore, hardware acceleration is proposed and implemented on NEON-FPGA processor using NE10 and CEPHES library. Findings The heuristic analysis of the algorithm using timing analysis and resource usage is presented. It has been observed that FFT execution time is reduced by 61% by boosting the performance of the algorithm and speed of multiplication operation has been doubled because of the optimization. Originality/value Very few literatures have presented the FPGA-based SAR imaging implementation, where analysis of windowing technique was a major interest. This is a unique approach to implement the SAR CSA using a hybrid approach of hardware–software integration on Zynq FPGA. The timing analysis propagates that it is suitable to use this model for real-time SAR applications.
Bibliographie:ObjectType-Article-1
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ISSN:0305-6120
1758-602X
DOI:10.1108/CW-02-2020-0031