Rapidly trainable and shallow-compiled quantum approximate optimization algorithm for maximum likelihood detection
In multiple-input and multiple-output (MIMO) systems, the maximum likelihood (ML) detection problem is NP-hard and becomes increasingly complex with more transmitting antennas and symbols. The quantum approximate optimization algorithm (QAOA), a leading candidate algorithm running in the noisy inter...
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| Vydáno v: | Physics letters. A Ročník 548; s. 130541 |
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| Hlavní autoři: | , , , , |
| Médium: | Journal Article |
| Jazyk: | angličtina |
| Vydáno: |
Elsevier B.V
15.07.2025
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| Témata: | |
| ISSN: | 0375-9601 |
| On-line přístup: | Získat plný text |
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| Shrnutí: | In multiple-input and multiple-output (MIMO) systems, the maximum likelihood (ML) detection problem is NP-hard and becomes increasingly complex with more transmitting antennas and symbols. The quantum approximate optimization algorithm (QAOA), a leading candidate algorithm running in the noisy intermediate-scale quantum (NISQ) devices, can show quantum advantage for approximately solving combinatorial optimization problems. In this paper, we propose an improved QAOA based maximum likelihood detection. In the proposed scheme, we use ZX-calculus to prove the parameter symmetry in QAOA circuits, which can be used to reduce the search space and accelerate the training process. Moreover, to run QAOA on quantum devices, an improved qubit mapping method with simultaneous gate absorption is proposed, which can compile the quantum circuit of the QAOA to satisfy the connectivity constraints of real quantum devices with fewer CNOT counts. In numerical experiments, our scheme accelerates parameter training by an average of 29.8% and uses fewer CNOT gates and shallower circuit depth during compilation. This demonstrates that our scheme has significant advantages over the traditional scheme.
•Use ZX-calculus to demonstrate the symmetry of parameters, which can be leveraged to accelerate parameter training.•Propose a circuit optimization enhanced qubit mapping method to reduce the number of CNOT gates during circuit compilation.•Simulations show the scheme boosts training speed and reduces CNOT count and circuit depth during compilation. |
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| ISSN: | 0375-9601 |
| DOI: | 10.1016/j.physleta.2025.130541 |