Wang, J., Shi, Y., Chen, Z., & Wen, M. (2025). SpikeFlow: A hardware–software co-designed systolic array for spiking neural networks. Journal of systems architecture, 169, 103604. https://doi.org/10.1016/j.sysarc.2025.103604
Citácia podle Chicago (17th ed.)Wang, Jianan, Yang Shi, Zhaoyun Chen, a Mei Wen. "SpikeFlow: A Hardware–software Co-designed Systolic Array for Spiking Neural Networks." Journal of Systems Architecture 169 (2025): 103604. https://doi.org/10.1016/j.sysarc.2025.103604.
Citácia podľa MLA (8th ed.)Wang, Jianan, et al. "SpikeFlow: A Hardware–software Co-designed Systolic Array for Spiking Neural Networks." Journal of Systems Architecture, vol. 169, 2025, p. 103604, https://doi.org/10.1016/j.sysarc.2025.103604.
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