SpikeFlow: A hardware–software co-designed systolic array for spiking neural networks

Spiking neural networks (SNNs), often referred to as third-generation neural networks, offer substantial advantages in efficiency and power consumption, which have led to their widespread use in both research and commercial applications. Additionally, the distinctive structure of SNNs not only inspi...

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Veröffentlicht in:Journal of systems architecture Jg. 169; S. 103604
Hauptverfasser: Wang, Jianan, Shi, Yang, Chen, Zhaoyun, Wen, Mei
Format: Journal Article
Sprache:Englisch
Veröffentlicht: Elsevier B.V 01.12.2025
Schlagworte:
Inference
Leaky integrate and fire
Sparse
Spiking neural network
Systolic array
Temporal-parallel dataflow
Systolic array
Inference
Sparse
Spiking neural network
Leaky integrate and fire
Temporal-parallel dataflow
ISSN:1383-7621
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Zusammenfassung:Spiking neural networks (SNNs), often referred to as third-generation neural networks, offer substantial advantages in efficiency and power consumption, which have led to their widespread use in both research and commercial applications. Additionally, the distinctive structure of SNNs not only inspires novel hardware designs but also presents challenges, particularly due to their sparse and temporal properties. The ability to fully exploit both temporal and sparse properties has a decisive impact on the execution efficiency of SNNs. However, existing neural network accelerator designs primarily focus on spatial-parallel dataflow mapping, with little attention given to temporal-parallelism in SNN accelerators. This makes it a struggle to map the temporal-parallel data flow of SNNs onto Systolic Array architecture. Specifically, temporal-parallel dataflow mapping, highly sparse 1-bit data, and specialized Leaky Integrate-and-Fire (LIF) activation units present significant challenges for optimization schemes and hardware architecture design. To address these obstacles, we first analyzed the temporal-parallel dataflows of SNNs and the hardware architecture of the Systolic Array architecture. Analysis reveals that the core issue lies in the mismatch between the number of total timesteps in SNNs and the parallel computing capabilities of hardware. We propose SpikeFlow, an optimization scheme for SNNs with temporal-parallel dataflows, consisting of software optimization of dataflow mapping and sparse algorithms, and hardware optimization for Systolic Array based accelerators. In terms of software optimization, SpikeFlow flexibly adjusts the mixed temporal–spatial dataflows and combines them with the corresponding Silence Cells strategy to improve the utilization of PE arrays and effectively exploit sparse data. For hardware, SpikeFlow provides collaborative and combinatorial optimization in the linear computation and data activation modules, while effectively supporting the corresponding dataflow mapping and sparse algorithms. SpikeFlow improves the execution efficiency of SNN inference tasks in an energy-efficient manner. Experiments show that SpikeFlow improves efficiency by up to 1.66X compared to common Systolic Array accelerators in SNN inference tasks. Furthermore, SpikeFlow reduces the chip area by 47.23% and power consumption by 46.86%. These results demonstrate that SpikeFlow offers significant advantages in hardware and software execution schemes for SNN-based inference. •We address the conflict between temporal-parallel dataflows and hardware design in SNNs.•We proposed SpikeFlow, a hardware–software co-designed Systolic Array for SNNs.•SpikeFlow flexibly adapts mixed dataflows and integrates sparse optimization strategies.•Spikeflow provides collaborative and combinatorial optimization in hardware design.•SpikeFlow demonstrates advantages in execution efficiency, energy overhead, and chip area.
ISSN:1383-7621
DOI:10.1016/j.sysarc.2025.103604