A streaming algorithm and hardware accelerator to estimate the empirical entropy of network flows
The empirical entropy is used in network traffic monitoring and classification to detect anomalous events and manage network resources. Computing the entropy of high-speed traffic in real time requires dedicated hardware, such as programmable switches and FPGA-based accelerators. While these devices...
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| Published in: | Computer networks (Amsterdam, Netherlands : 1999) Vol. 237; p. 110035 |
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| Main Authors: | , , , , , |
| Format: | Journal Article |
| Language: | English |
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Elsevier B.V
01.12.2023
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| ISSN: | 1389-1286, 1872-7069 |
| Online Access: | Get full text |
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| Abstract | The empirical entropy is used in network traffic monitoring and classification to detect anomalous events and manage network resources. Computing the entropy of high-speed traffic in real time requires dedicated hardware, such as programmable switches and FPGA-based accelerators. While these devices can achieve high performance by exploiting the parallelism of the algorithm, they possess limited on-chip storage. Thus, designing algorithms that estimate the entropy of network traffic with low error and memory usage is challenging. In this paper, we present an entropy-estimation streaming algorithm that operates on large datasets with sublinear memory usage. We use sketches to estimate the frequency and cardinality of network flows during an observation interval. We only store the frequencies of the most frequent flows and use them to estimate the rest of the frequencies by assuming a power-law distribution. Our results show that, using real network traces with observation intervals of up to 50 million flows, we can estimate their empirical entropy with 0.69% mean relative error, using more than three orders of magnitude less memory than an exact entropy-computation method. We also present an FPGA-based hardware accelerator for the algorithm that can operate at a line rate of more than 200 Gbps and an estimation latency of 16μs. Using fixed-point arithmetic and function approximations in the accelerator increases the mean estimation error of our algorithm by only 0.07%.
•An algorithm that measures and models traffic to estimate its empirical entropy.•Algorithm achieves 0.69% error on large traces using sketches and a power-law fit.•Accelerator architecture exploits parallelism and optimizes on-chip memory usage.•FPGA implementation operates at line rate of 200 Gbps with 16 us estimation latency. |
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| AbstractList | The empirical entropy is used in network traffic monitoring and classification to detect anomalous events and manage network resources. Computing the entropy of high-speed traffic in real time requires dedicated hardware, such as programmable switches and FPGA-based accelerators. While these devices can achieve high performance by exploiting the parallelism of the algorithm, they possess limited on-chip storage. Thus, designing algorithms that estimate the entropy of network traffic with low error and memory usage is challenging. In this paper, we present an entropy-estimation streaming algorithm that operates on large datasets with sublinear memory usage. We use sketches to estimate the frequency and cardinality of network flows during an observation interval. We only store the frequencies of the most frequent flows and use them to estimate the rest of the frequencies by assuming a power-law distribution. Our results show that, using real network traces with observation intervals of up to 50 million flows, we can estimate their empirical entropy with 0.69% mean relative error, using more than three orders of magnitude less memory than an exact entropy-computation method. We also present an FPGA-based hardware accelerator for the algorithm that can operate at a line rate of more than 200 Gbps and an estimation latency of 16μs. Using fixed-point arithmetic and function approximations in the accelerator increases the mean estimation error of our algorithm by only 0.07%.
•An algorithm that measures and models traffic to estimate its empirical entropy.•Algorithm achieves 0.69% error on large traces using sketches and a power-law fit.•Accelerator architecture exploits parallelism and optimizes on-chip memory usage.•FPGA implementation operates at line rate of 200 Gbps with 16 us estimation latency. |
| ArticleNumber | 110035 |
| Author | Vera, Sofía Soto, Javier E. Figueroa, Miguel Fernández, Yaime Prieto, Yasmany Hernández, Cecilia |
| Author_xml | – sequence: 1 givenname: Yaime orcidid: 0000-0002-4013-0745 surname: Fernández fullname: Fernández, Yaime email: yfernandezj@udec.cl organization: Electrical Engineering Department, Universidad de Concepción, Chile – sequence: 2 givenname: Javier E. orcidid: 0000-0002-6057-0094 surname: Soto fullname: Soto, Javier E. email: javsoto@udec.cl organization: Electrical Engineering Department, Universidad de Concepción, Chile – sequence: 3 givenname: Sofía orcidid: 0009-0008-3830-7821 surname: Vera fullname: Vera, Sofía email: svera2017@udec.cl organization: Electrical Engineering Department, Universidad de Concepción, Chile – sequence: 4 givenname: Yasmany orcidid: 0000-0002-6827-2657 surname: Prieto fullname: Prieto, Yasmany email: yprieto@ucsc.cl organization: Computer Science Department, Universidad Católica de la Santísima Concepción, Chile – sequence: 5 givenname: Cecilia orcidid: 0000-0003-1301-6987 surname: Hernández fullname: Hernández, Cecilia email: cecihernandez@udec.cl organization: Computer Science Department, Universidad de Concepción, Chile – sequence: 6 givenname: Miguel orcidid: 0000-0002-5033-432X surname: Figueroa fullname: Figueroa, Miguel email: mifiguer@udec.cl organization: Electrical Engineering Department, Universidad de Concepción, Chile |
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| Keywords | Shannon empirical entropy Hardware acceleration Sketch-based streaming algorithms |
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