Design and Implementation of Low Power, Area Crosstalk Reduction Using Static Timing Analysis

One of the biggest issues with VLSI connections is crosstalk, which is caused by coupling capacitance. Crosstalk reduces operation performance during switching activities and produces undesired output. Noise level rises as switching frequency does as well. Crosstalk will be eliminated by encode the...

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Veröffentlicht in:E3S web of conferences Jg. 540; S. 14001
Hauptverfasser: Obulesu, Battari, Ashok, P., Rajesh, J., Madhu, K., Rakesh, G., Raghava Sarath Chandra Reddy, Guddety
Format: Journal Article Tagungsbericht
Sprache:Englisch
Veröffentlicht: Les Ulis EDP Sciences 01.01.2024
Schlagworte:
bus decoder,very large scale integrated (vlsi)circuit
bus encoder
Capacitance
Computer engineering
Crosstalk
crosstalk probability detector
Design
Integrated circuits
Noise levels
Optimization
Optimization techniques
Power consumption
Static timing analysis
Wave division multiplexing
India
ISSN:2267-1242, 2555-0403, 2267-1242
Online-Zugang:Volltext
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Zusammenfassung:One of the biggest issues with VLSI connections is crosstalk, which is caused by coupling capacitance. Crosstalk reduces operation performance during switching activities and produces undesired output. Noise level rises as switching frequency does as well. Crosstalk will be eliminated by encode the data before connecting into the bus line. This procedure reduces the crosstalk issue by using the improved logic architecture. The proposed approach utilizes a combination of circuit-level optimization techniques, such as gate sizing and interconnect optimization, and advanced timing analysis tools to minimize power consumption and reduce crosstalk.
Bibliographie:ObjectType-Conference Proceeding-1
SourceType-Conference Papers & Proceedings-1
content type line 21
ISSN:2267-1242
2555-0403
2267-1242
DOI:10.1051/e3sconf/202454014001