Full-Array Boolean Logic CIM Macro With Self-Recycling 10T-SRAM Cell for AES Systems

Computing in memory (CIM), which alleviates the need to transfer a large amount of data between processor and memory, significantly reducing latency and energy consumption, is a promising new computing architecture for addressing the von Neumann bottleneck problem. This article proposes a CIM array...

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Published in:IEEE transactions on very large scale integration (VLSI) systems Vol. 33; no. 8; pp. 2214 - 2224
Main Authors: Li, Xin, Pan, Ying, Jin, Qian, Chen, Lintao, Lou, Yang, Wu, Baofa, Long, Jiajun, Zhou, Yongliang, Peng, Chunyu, Wu, Xiulong, Lin, Zhiting
Format: Journal Article
Language:English
Published: New York IEEE 01.08.2025
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:
Arrays
Boolean
Common Information Model (computing)
Computation
Computer architecture
Data processing
Encryption
Energy consumption
Full-array activation
in-memory logical operation
Logic arrays
Memory management
Microprocessors
Power demand
Random access memory
self-recycling technology
Static random access memory
static random-access memory (SRAM)
Throughput
Transistors
von Neumann architecture
Writing
ISSN:1063-8210, 1557-9999
Online Access:Get full text
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Summary:Computing in memory (CIM), which alleviates the need to transfer a large amount of data between processor and memory, significantly reducing latency and energy consumption, is a promising new computing architecture for addressing the von Neumann bottleneck problem. This article proposes a CIM array structure composed of self-recycling 10T static random access memory (SRAM) cells, which can realize orthogonal data writing, and multiple Boolean logical operations for the entire array. The self-recycling and full-array activation characteristics are extremely suitable for accelerating diverse data processing algorithms such as the Advanced Encryption Standard (AES). A 4-kb SRAM is implemented in 55-nm CMOS technology to verify the effectiveness of the design. Compared with other state-of-the-art architectures, the throughput and the operating frequency of the proposed CIM macro are increased to 843 GOPS/kb (<inline-formula> <tex-math notation="LaTeX">2.64\times </tex-math></inline-formula>) and 823.7 MHz (<inline-formula> <tex-math notation="LaTeX">2.6\times </tex-math></inline-formula>), respectively. The energy efficiency reaches 246.9 TOPS/W. When applied to the AES, the energy consumption is 35.77% less than the digital CIM architecture that is not self-recycling.
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ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2025.3572140