Stochastic-Binary Hybrid Spatial Coding Multiplier for Convolutional Neural Network Accelerator

Convolutional neural networks have remarkable performance in artificial intelligence, although at the cost of computationally demanding processes within a single inference. Simultaneously, the underlying chip process is reaching its constraints as Moore's law diminishes. Stochastic computation,...

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Vydané v:	IEEE transactions on nanotechnology Ročník 23; s. 600 - 605
Hlavní autori:	Zhou, Yakun, Yan, Jiajun, Zhou, Yizhuo, Shao, Ziyang, Chen, Jienan
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	New York IEEE 2024 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:	Arithmetic Artificial intelligence Artificial neural networks Binary codes Biological neural networks bit segment Coding Encoding Energy dissipation Error compensation Extension-uniform multiplier Fixed point arithmetic Fixed points (mathematics) Gates (circuits) Hardware Logic circuits Logic gates Moore's law Multipliers Neural networks parallel spatial coding stochastic-binary domain Wire
ISSN:	1536-125X, 1941-0085
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Shrnutí:	Convolutional neural networks have remarkable performance in artificial intelligence, although at the cost of computationally demanding processes within a single inference. Simultaneously, the underlying chip process is reaching its constraints as Moore's law diminishes. Stochastic computation, as a hardware-friendly and unconventional approach, can alleviate the burden of sophisticated arithmetic at the circuit level. This work presents a novel stochastic computing (SC) multiplier that employs an extension-uniform approach to create bit sequences without relying on logical gates. In addition, we propose a stochastic-binary domain arithmetic method to achieve low-cost hardware implementation and low power dissipation. The 4n-bit widths are partitioned into n 4-bit widths, with the high-precision components executed in the binary domain and the low-precision components executed in the stochastic domain. Additionally, a hardware-compatible circuit for compensating faults is also introduced. The accelerator on cifar10 using stochastic binary hybrid domain spatial coding (SHSC) multiplier achieves better performance than the fixed-point counterpart, with a 33.7% reduction in area and 23% reduction in power.
Bibliografia:	ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 14
ISSN:	1536-125X 1941-0085
DOI:	10.1109/TNANO.2024.3444278