HTs-GCN: Identifying Hardware Trojan Nodes in Integrated Circuits Using a Graph Convolutional Network

Hardware Trojans (HTs) present significant security threats to integrated circuits. Detecting and locating HTs is crucial for mitigating these threats. Thus, this article proposes a method called HTs-GCN, which utilizes a graph convolutional network (GCN) to identify HTs. First, it extracts two nove...

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Veröffentlicht in:IEEE transactions on computer-aided design of integrated circuits and systems Jg. 44; H. 6; S. 2353 - 2366
Hauptverfasser: Xiao, Jie, Chai, Shuiliang, Gao, Yanjiao, Huang, Yuhao, Zhang, Fan, Chen, Tieming
Format: Journal Article
Sprache:Englisch
Veröffentlicht: New York IEEE 01.06.2025
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:
Artificial neural networks
Benchmark testing
Benchmarks
Data balancing
Design automation
Feature extraction
feature fusion
Hardware
hardware Trojans (HTs)
Integrated circuit modeling
Integrated circuits
Location awareness
Logic gates
Message passing
Network security
node features
Nodes
Recall
Trojan horses
ISSN:0278-0070, 1937-4151
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Zusammenfassung:Hardware Trojans (HTs) present significant security threats to integrated circuits. Detecting and locating HTs is crucial for mitigating these threats. Thus, this article proposes a method called HTs-GCN, which utilizes a graph convolutional network (GCN) to identify HTs. First, it extracts two novel features of gate nodes using a depth-first search strategy and topological logical analysis to enrich the feature information of circuit nodes. Second, through a message-passing mechanism, it designs a local feature aggregation method based on the GCN and a global feature fusion method based on an attention mechanism to improve the representation capability of circuit node features. Then, leveraging the concept of stochastic gradient descent and incorporating mini-batch oversampling and under-sampling techniques, it employs a dataset imbalance handling method to address the scarcity of HT nodes in circuits. These approaches significantly enhance the distinguishability between gate nodes with HTs and other gate nodes while reducing computational complexity. Experimental results indicate that HTs-GCN outperforms the recently proposed NHTD-GL method in terms of recall: it achieves approximately 7.8% points higher recall while maintaining similar accuracy. HTs-GCN demonstrates exceptional generalizability, with an average recall and accuracy of 93.0% and 100%, respectively, on infrequently used circuits in the Trust-Hub benchmark. In addition, on the TRIT-TC benchmark, HTs-GCN achieves excellent average true positive rate (TPR) and true negative rate (TNR) of 95.1% and 94.4%, respectively. Furthermore, HTs-GCN exhibits robust performance under gate modification attacks, with average TPR and TNR reaching 82.1% and 92.5%, respectively.
Bibliographie:ObjectType-Article-1
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ISSN:0278-0070
1937-4151
DOI:10.1109/TCAD.2024.3520522