A Robust FPGA Router With Optimization of High-Fanout Nets and Intra-CLB Connections

Routing is the most time-consuming step in the implementation flow of field programmable gate array (FPGA) designs. With the advance in transistor scaling and system integration, hardware resources in FPGA devices are growing in a larger quantity and diversity. The routing architecture is designed t...

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Vydané v:IEEE transactions on computer-aided design of integrated circuits and systems Ročník 44; číslo 3; s. 1003 - 1016
Hlavní autori: Jiang, Xun, Wang, Jiarui, Mai, Jing, Di, Zhixiong, Lin, Yibo
Médium: Journal Article
Jazyk:English
Vydavateľské údaje: New York IEEE 01.03.2025
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:
Algorithms
Benchmarks
Computer architecture
Congestion
Fanout
Field programmable gate arrays
Integer linear programming
Logic
Partitioning algorithms
Routing
Solution space
Steiner trees
ISSN:0278-0070, 1937-4151
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Shrnutí:Routing is the most time-consuming step in the implementation flow of field programmable gate array (FPGA) designs. With the advance in transistor scaling and system integration, hardware resources in FPGA devices are growing in a larger quantity and diversity. The routing architecture is designed to be more complicated for mapping RTL designs to FPGA devices correctly, which brings significant challenges for current FPGA routing algorithms. The key challenges for routing algorithms lie in large solution space and heavy congestion, especially for high-fanout nets (HFNets). We propose a partition-based algorithm to accelerate the routing of HFNets, which decomposes the global routing guide to shrink the search space for connecting each sink. Meanwhile, the congestions existing inside configurable logic block (CLB) are hard to handle by traditional sequential negotiation-based algorithms, because the industrial routing architecture is quite complex. We propose a concurrent intra-CLB rerouting algorithm to effectively resolve routing congestion inside a CLB tile induced by connections between intra-CLB logic pins, e.g., logic elements and switch boxes. Experimental results on modified ISPD2016 benchmarks demonstrate that our framework can achieve 100% routability in 9.8% less wirelength and <inline-formula> <tex-math notation="LaTeX">11\times </tex-math></inline-formula> less runtime, while the state-of-the-art VTR 8.0 routing algorithm fails at 7 of 12 benchmarks.
Bibliografia:ObjectType-Article-1
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content type line 14
ISSN:0278-0070
1937-4151
DOI:10.1109/TCAD.2024.3447218