Optimization of Multisymbol Architecture of the Entropy Coder for H.265/HEVC Video Encoders
Video compression takes advantage of entropy coding based on binary arithmetic coding to achieve lower-bit rates. On the other hand, the throughput of hardware implementations is limited by intersymbol dependencies existing in the entropy coding. This article presents a series of optimizations appli...
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| Vydáno v: | IEEE transactions on computer-aided design of integrated circuits and systems Ročník 44; číslo 2; s. 458 - 468 |
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| Hlavní autor: | |
| Médium: | Journal Article |
| Jazyk: | angličtina |
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New York
IEEE
01.02.2025
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Témata: | |
| ISSN: | 0278-0070, 1937-4151 |
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| Abstract | Video compression takes advantage of entropy coding based on binary arithmetic coding to achieve lower-bit rates. On the other hand, the throughput of hardware implementations is limited by intersymbol dependencies existing in the entropy coding. This article presents a series of optimizations applied to the architecture of the entropy coder presented in previous studies. The reference architecture uses several parallel processing paths for serialization, binarization, and probability model (PM) adaptation. Within this study, the paths are modified by increasing the number of symbols processed in one clock cycle and enlarging buffers. The throughput is also improved by more efficient multiplexing between paths. The parallelism of the PM adaptation is increased to eight and seven symbols per clock cycle for significance map and greater-than-1 contexts, respectively. Critical paths associated with state transitions are shortened by changing probability state representation from natural binary code to unary one. The optimized entropy coder increases the average symbol rate from 16.22 to 33.19 bins per clock cycle for high-quality low-delay H.265/HEVC compression. The optimized design for TSMC 65nm technology consumes 458.51k gates and can operate at 666 MHz, allowing for a throughput of 22 014 Mbins/s. |
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| AbstractList | Video compression takes advantage of entropy coding based on binary arithmetic coding to achieve lower-bit rates. On the other hand, the throughput of hardware implementations is limited by intersymbol dependencies existing in the entropy coding. This article presents a series of optimizations applied to the architecture of the entropy coder presented in previous studies. The reference architecture uses several parallel processing paths for serialization, binarization, and probability model (PM) adaptation. Within this study, the paths are modified by increasing the number of symbols processed in one clock cycle and enlarging buffers. The throughput is also improved by more efficient multiplexing between paths. The parallelism of the PM adaptation is increased to eight and seven symbols per clock cycle for significance map and greater-than-1 contexts, respectively. Critical paths associated with state transitions are shortened by changing probability state representation from natural binary code to unary one. The optimized entropy coder increases the average symbol rate from 16.22 to 33.19 bins per clock cycle for high-quality low-delay H.265/HEVC compression. The optimized design for TSMC 65nm technology consumes 458.51k gates and can operate at 666 MHz, allowing for a throughput of 22 014 Mbins/s. |
| Author | Pastuszak, Grzegorz |
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| SubjectTerms | Adaptation Adaptation models Architecture design Arithmetic coding Binary codes Clocks Coders Computer architecture Entropy entropy coding field-programmable gate array (FPGA) H.265/HEVC Multiplexing Parallel processing Registers Symbols Throughput UHDTV Video compression |
| Title | Optimization of Multisymbol Architecture of the Entropy Coder for H.265/HEVC Video Encoders |
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