Parallel Interleaver Design for a High throughput HSPA+/LTE Multi-Standard Turbo Decoder

To meet the evolving data rate requirements of emerging wireless communication technologies, many parallel architectures have been proposed to implement high throughput turbo decoders. However, concurrent memory reading/writing in parallel turbo decoding architectures leads to severe memory conflict...

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Vydané v:	IEEE transactions on circuits and systems. I, Regular papers Ročník 61; číslo 5; s. 1376 - 1389
Hlavní autori:	Guohui Wang, Hao Shen, Yang Sun, Cavallaro, Joseph R., Vosoughi, Aida, Yuanbin Guo
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	New York IEEE 01.05.2014 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:	Architecture ASIC implementation Circuits Clocks CMOS Computer architecture Concurrent processing Decoders Decoding Hardware HSPA interleaver Long Term Evolution LTE/LTE-advanced memory contention parallel processing Throughput turbo decoder VLSI architecture Wireless communication Wireless communications
ISSN:	1549-8328, 1558-0806
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