APA (7th ed.) Citation

Chenini, H., Dérutin, J. P., Aufrère, R., & Chapuis, R. (2013). Parallel embedded processor architecture for FPGA-based image processing using parallel software skeletons. EURASIP journal on advances in signal processing, 2013(1), . https://doi.org/10.1186/1687-6180-2013-153

Chicago Style (17th ed.) Citation

Chenini, Hanen, Jean Pierre Dérutin, Romuald Aufrère, and Roland Chapuis. "Parallel Embedded Processor Architecture for FPGA-based Image Processing Using Parallel Software Skeletons." EURASIP Journal on Advances in Signal Processing 2013, no. 1 (2013). https://doi.org/10.1186/1687-6180-2013-153.

MLA (9th ed.) Citation

Chenini, Hanen, et al. "Parallel Embedded Processor Architecture for FPGA-based Image Processing Using Parallel Software Skeletons." EURASIP Journal on Advances in Signal Processing, vol. 2013, no. 1, 2013, https://doi.org/10.1186/1687-6180-2013-153.