A Multiple-Stream Registerless Shared-Resource Processor

A novel high-performance processor architecture for processing a large number of independent instruction streams is proposed and its operating behavior studied. The proposed processor operates on instruction words in a two-address format (thereby eliminating the "operating registers"), and...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on computers Vol. C-23; no. 3; pp. 277 - 285
Main Author: Miller, E.F.
Format: Journal Article
Language:English
Published: IEEE 01.03.1974
Subjects:
Computational modeling
Computer architecture
computer instruction stream models
Computers
Costs
Finite element analysis
Instruction sets
Memory management
multiple data stream (MIMD) queued instruction processing
multiple instruction stream
Registers
Resource management
resource-sharing
Streams
Throughput
two-address format
ISSN:0018-9340, 1557-9956
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:A novel high-performance processor architecture for processing a large number of independent instruction streams is proposed and its operating behavior studied. The proposed processor operates on instruction words in a two-address format (thereby eliminating the "operating registers"), and is organized in a fashion which permits as high degree of internal buffering and pipelining. The processor has the following properties: 1) The hardware cost grows only slightly more than linearly with the overall implementation cost; 2) The overall performance is primarily dependent on the processor wordtime and is only secondarily dependent on the supporting memory cycle time; 3) All instruction stream interfaces with memory occur at special queuing (buffer) units which are used to "unscramble" the instruction streams and continually provide work for subsequent processing elements.
ISSN:0018-9340
1557-9956
DOI:10.1109/T-C.1974.223923