A 0.65-V 12-16-GHz Sub-Sampling PLL With 56.4-fsrms Integrated Jitter and −256.4-dB FoM

This article presents a low-voltage (LV) sub-sampling phase-locked loop (LVSSPLL). The architecture of hybrid dual-path loop-based SSPLL is proposed to mitigate the issue of limited output voltage range of LV charge pump (CP). Four LV building blocks, including a proportional path sub-sampling CP (S...

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Vydané v:	IEEE journal of solid-state circuits Ročník 55; číslo 6; s. 1665 - 1683
Hlavní autori:	Zhang, Zhao, Zhu, Guang, Patrick Yue, C.
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	New York IEEE 01.06.2020 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:	Capacitors Charge pumps Clocks CMOS Detectors Digitally controlled capacitor array (DCCA) hybrid dual-path loop Jitter low jitter low supply voltage Microprocessors Phase detectors Phase locked loops Phase locked systems Phase noise Power consumption Sampling sub-sampling charge pump (SSCP) sub-sampling phase detector (SSPD) sub-sampling phase-locked loop (SSPLL) Vibration Voltage controlled oscillators
ISSN:	0018-9200, 1558-173X
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Abstract	This article presents a low-voltage (LV) sub-sampling phase-locked loop (LVSSPLL). The architecture of hybrid dual-path loop-based SSPLL is proposed to mitigate the issue of limited output voltage range of LV charge pump (CP). Four LV building blocks, including a proportional path sub-sampling CP (SSCP), an integral path SSCP, an LV sub-sampling phase detector, and an LV digitally controlled capacitor array in the LC -based voltage-controlled oscillator, are proposed to simultaneously reduce the PLL integrated jitter and the jitter variation over supply voltage variation. Fabricated in 40-nm CMOS process with a core active area of 0.24 mm 2 , the LVSSPLL operates at 0.65-V supply and achieves 12-16-GHz tuning range, 56.4-fs integrated jitter at 14 GHz, 7.2-mW power consumption, and −256.4-dB figure-of-merit (FoM). The measured integrated jitter variation is less than 14.5 fs within the supply voltage range from 0.62 to 0.7 V, which shows robustness over supply voltage variation.
AbstractList	This article presents a low-voltage (LV) sub-sampling phase-locked loop (LVSSPLL). The architecture of hybrid dual-path loop-based SSPLL is proposed to mitigate the issue of limited output voltage range of LV charge pump (CP). Four LV building blocks, including a proportional path sub-sampling CP (SSCP), an integral path SSCP, an LV sub-sampling phase detector, and an LV digitally controlled capacitor array in the LC -based voltage-controlled oscillator, are proposed to simultaneously reduce the PLL integrated jitter and the jitter variation over supply voltage variation. Fabricated in 40-nm CMOS process with a core active area of 0.24 mm 2 , the LVSSPLL operates at 0.65-V supply and achieves 12-16-GHz tuning range, 56.4-fs integrated jitter at 14 GHz, 7.2-mW power consumption, and −256.4-dB figure-of-merit (FoM). The measured integrated jitter variation is less than 14.5 fs within the supply voltage range from 0.62 to 0.7 V, which shows robustness over supply voltage variation. This article presents a low-voltage (LV) sub-sampling phase-locked loop (LVSSPLL). The architecture of hybrid dual-path loop-based SSPLL is proposed to mitigate the issue of limited output voltage range of LV charge pump (CP). Four LV building blocks, including a proportional path sub-sampling CP (SSCP), an integral path SSCP, an LV sub-sampling phase detector, and an LV digitally controlled capacitor array in the LC -based voltage-controlled oscillator, are proposed to simultaneously reduce the PLL integrated jitter and the jitter variation over supply voltage variation. Fabricated in 40-nm CMOS process with a core active area of 0.24 mm2, the LVSSPLL operates at 0.65-V supply and achieves 12–16-GHz tuning range, 56.4-fs integrated jitter at 14 GHz, 7.2-mW power consumption, and −256.4-dB figure-of-merit (FoM). The measured integrated jitter variation is less than 14.5 fs within the supply voltage range from 0.62 to 0.7 V, which shows robustness over supply voltage variation.
Author	Patrick Yue, C. Zhang, Zhao Zhu, Guang
Author_xml	– sequence: 1 givenname: Zhao orcidid: 0000-0002-9009-9045 surname: Zhang fullname: Zhang, Zhao email: parkerzz@foxmail.com organization: Department of Electronic and Computer Engineering, Hong Kong University of Science and Technology, Hong Kong – sequence: 2 givenname: Guang orcidid: 0000-0001-9970-4988 surname: Zhu fullname: Zhu, Guang organization: Department of Electronic and Computer Engineering, Hong Kong University of Science and Technology, Hong Kong – sequence: 3 givenname: C. surname: Patrick Yue fullname: Patrick Yue, C. email: eepatrick@ust.hk organization: Department of Electronic and Computer Engineering, Hong Kong University of Science and Technology, Hong Kong
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Snippet	This article presents a low-voltage (LV) sub-sampling phase-locked loop (LVSSPLL). The architecture of hybrid dual-path loop-based SSPLL is proposed to...
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SubjectTerms	Capacitors Charge pumps Clocks CMOS Detectors Digitally controlled capacitor array (DCCA) hybrid dual-path loop Jitter low jitter low supply voltage Microprocessors Phase detectors Phase locked loops Phase locked systems Phase noise Power consumption Sampling sub-sampling charge pump (SSCP) sub-sampling phase detector (SSPD) sub-sampling phase-locked loop (SSPLL) Vibration Voltage controlled oscillators
Title	A 0.65-V 12-16-GHz Sub-Sampling PLL With 56.4-fsrms Integrated Jitter and −256.4-dB FoM
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