A 0.65-V 12-16-GHz Sub-Sampling PLL With 56.4-fsrms Integrated Jitter and −256.4-dB FoM
This article presents a low-voltage (LV) sub-sampling phase-locked loop (LVSSPLL). The architecture of hybrid dual-path loop-based SSPLL is proposed to mitigate the issue of limited output voltage range of LV charge pump (CP). Four LV building blocks, including a proportional path sub-sampling CP (S...
Gespeichert in:
| Veröffentlicht in: | IEEE journal of solid-state circuits Jg. 55; H. 6; S. 1665 - 1683 |
|---|---|
| Hauptverfasser: | , , |
| Format: | Journal Article |
| Sprache: | Englisch |
| Veröffentlicht: |
New York
IEEE
01.06.2020
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Schlagworte: | |
| ISSN: | 0018-9200, 1558-173X |
| Online-Zugang: | Volltext |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| Zusammenfassung: | This article presents a low-voltage (LV) sub-sampling phase-locked loop (LVSSPLL). The architecture of hybrid dual-path loop-based SSPLL is proposed to mitigate the issue of limited output voltage range of LV charge pump (CP). Four LV building blocks, including a proportional path sub-sampling CP (SSCP), an integral path SSCP, an LV sub-sampling phase detector, and an LV digitally controlled capacitor array in the LC -based voltage-controlled oscillator, are proposed to simultaneously reduce the PLL integrated jitter and the jitter variation over supply voltage variation. Fabricated in 40-nm CMOS process with a core active area of 0.24 mm 2 , the LVSSPLL operates at 0.65-V supply and achieves 12-16-GHz tuning range, 56.4-fs integrated jitter at 14 GHz, 7.2-mW power consumption, and −256.4-dB figure-of-merit (FoM). The measured integrated jitter variation is less than 14.5 fs within the supply voltage range from 0.62 to 0.7 V, which shows robustness over supply voltage variation. |
|---|---|
| Bibliographie: | ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 14 |
| ISSN: | 0018-9200 1558-173X |
| DOI: | 10.1109/JSSC.2020.2967562 |