APA (7th ed.) Citation

Zhang, Z., Zhu, G., & Patrick Yue, C. (2020). A 0.65-V 12-16-GHz Sub-Sampling PLL With 56.4-fsrms Integrated Jitter and −256.4-dB FoM. IEEE journal of solid-state circuits, 55(6), 1665-1683. https://doi.org/10.1109/JSSC.2020.2967562

Chicago Style (17th ed.) Citation

Zhang, Zhao, Guang Zhu, and C. Patrick Yue. "A 0.65-V 12-16-GHz Sub-Sampling PLL With 56.4-fsrms Integrated Jitter and −256.4-dB FoM." IEEE Journal of Solid-state Circuits 55, no. 6 (2020): 1665-1683. https://doi.org/10.1109/JSSC.2020.2967562.

MLA (9th ed.) Citation

Zhang, Zhao, et al. "A 0.65-V 12-16-GHz Sub-Sampling PLL With 56.4-fsrms Integrated Jitter and −256.4-dB FoM." IEEE Journal of Solid-state Circuits, vol. 55, no. 6, 2020, pp. 1665-1683, https://doi.org/10.1109/JSSC.2020.2967562.