Study of Data Security Algorithms using Verilog HDL
This paper describes an overview of data security algorithms and its performance evaluation. AES, RC5 and SHA algorithms have been taken under this study. Three different types of security algorithms used to analyze the performance study. The designs were implemented in Quartus-II software. The resu...
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| Vydáno v: | International journal of electrical and computer engineering (Malacca, Malacca) Ročník 5; číslo 5; s. 1092 |
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| Hlavní autoři: | , , |
| Médium: | Journal Article |
| Jazyk: | angličtina |
| Vydáno: |
Yogyakarta
IAES Institute of Advanced Engineering and Science
01.10.2015
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| ISSN: | 2088-8708, 2088-8708 |
| On-line přístup: | Získat plný text |
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| Shrnutí: | This paper describes an overview of data security algorithms and its performance evaluation. AES, RC5 and SHA algorithms have been taken under this study. Three different types of security algorithms used to analyze the performance study. The designs were implemented in Quartus-II software. The results obtained for encryption and decryption procedures show a significant improvement on the performance of the three algorithms. In this paper, 128-bit AES, 64-bit of RC5 and 512-bit of SHA256 encryption and Decryption has been made using Verilog Hardware Description Language and simulated using ModelSim. |
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| Bibliografie: | ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 14 |
| ISSN: | 2088-8708 2088-8708 |
| DOI: | 10.11591/ijece.v5i5.pp1092-1101 |