Synthesis of multilevel NAND gate circuits for incompletely specified multi-output Boolean functions and CAD using permissible cubes and PCRM graphs

A computer-aided design procedure for the automatic design of multilevel NAND gate logic networks as encountered in the synthesis of VLSI logic circuits is presented. A powerful technique using logic zero-one-interaction of permissible cubes is among the salient features in the synthesizing algorith...

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Bibliographic Details
Published in:International journal of electronics Vol. 78; no. 2; pp. 303 - 316
Main Authors: CHEN, LIANG-CHIA, TWU, HORNG-TAY
Format: Journal Article
Language:English
Published: London Taylor & Francis Group 01.02.1995
Taylor & Francis
Subjects:
Applied sciences
Circuit properties
Digital circuits
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Exact sciences and technology
ISSN:0020-7217, 1362-3060
Online Access:Get full text
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Summary:A computer-aided design procedure for the automatic design of multilevel NAND gate logic networks as encountered in the synthesis of VLSI logic circuits is presented. A powerful technique using logic zero-one-interaction of permissible cubes is among the salient features in the synthesizing algorithm developed. Only uncomplemented inputs are involved in this design technique, so fewer NAND gates are required in the synthesized logic network. The algorithm developed is feasible for any number of input variables and any incompletely specified functions. The algorithm is implemented in the C language using a software approach based on our powerful data structure that have also been developed. Permissible-cube-related-minterm (PCRM) graphs generate the set of required permissible cubes automatically. The automatic level-reduction and gate-reduction of logic networks using a CAD approach is also described. The CAD algorithms provide automatic synthesis of nearly minimal multilevel multi-output NAND gate logic networks.
ISSN:0020-7217
1362-3060
DOI:10.1080/00207219508926164