Design and Analysis of Low Power Reversible Majority Logic-Based Adder/Subtractor Circuits with Parallel Computing Optimization

The increasing circuit density in CMOS technology is often accompanied by rising power consumption, posing significant challenges in modern Very Large Scale Integration (VLSI) designs. As device dimensions continue to shrink, power dissipation and heat generation become major constraints, necessitat...

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Vydané v:	SN computer science Ročník 6; číslo 6; s. 645
Hlavní autori:	Potharaju, Vidya Sagar, Saminadan, V.
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	Singapore Springer Nature Singapore 01.08.2025 Springer Nature B.V
Predmet:	Adding circuits Circuits Computer Imaging Computer Science Computer Systems Organization and Communication Networks Data Structures and Information Theory Design Design optimization Energy dissipation Fault tolerance Garbage Gates (circuits) Heat generation Information Systems and Communication Service Large scale integration Literature reviews Logic Logic circuits Original Research Pattern Recognition and Graphics Performance evaluation Power efficiency Power management Quantum computing Research Advancements in Network Technologies Signal processing Software Engineering/Programming and Operating Systems Very large scale integration Vision CMOS Parallel computing Quantum Majority Gate and quantum computing Reversible logic Majority logic
ISSN:	2661-8907, 2662-995X, 2661-8907
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