Design and Analysis of Low Power Reversible Majority Logic-Based Adder/Subtractor Circuits with Parallel Computing Optimization

The increasing circuit density in CMOS technology is often accompanied by rising power consumption, posing significant challenges in modern Very Large Scale Integration (VLSI) designs. As device dimensions continue to shrink, power dissipation and heat generation become major constraints, necessitat...

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Vydáno v:SN computer science Ročník 6; číslo 6; s. 645
Hlavní autoři: Potharaju, Vidya Sagar, Saminadan, V.
Médium: Journal Article
Jazyk:angličtina
Vydáno: Singapore Springer Nature Singapore 01.08.2025
Springer Nature B.V
Témata:
Adding circuits
Circuits
Computer Imaging
Computer Science
Computer Systems Organization and Communication Networks
Data Structures and Information Theory
Design
Design optimization
Energy dissipation
Fault tolerance
Garbage
Gates (circuits)
Heat generation
Information Systems and Communication Service
Large scale integration
Literature reviews
Logic
Logic circuits
Original Research
Pattern Recognition and Graphics
Performance evaluation
Power efficiency
Power management
Quantum computing
Research Advancements in Network Technologies
Signal processing
Software Engineering/Programming and Operating Systems
Very large scale integration
Vision
CMOS
Parallel computing
Quantum Majority Gate and quantum computing
Reversible logic
Majority logic
ISSN:2661-8907, 2662-995X, 2661-8907
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Popis
Shrnutí:The increasing circuit density in CMOS technology is often accompanied by rising power consumption, posing significant challenges in modern Very Large Scale Integration (VLSI) designs. As device dimensions continue to shrink, power dissipation and heat generation become major constraints, necessitating the development of alternative computing paradigms. One promising solution is Reversible Logic Gate-based Implementation, which preserves information and minimizes energy loss. Another approach, Majority Logic in Approximate Computation Designs, reduces power by using fewer logic gates, ideal for error-tolerant applications. This work proposes a Quantum Majority Gate-Based Adder/Subtractor that integrates reversible logic with majority-based computation to achieve lower quantum cost, reduced garbage outputs, and improved scalability. Additionally, the design incorporates parallel computing optimization techniques, enabling high-speed arithmetic operations with reduced latency. Performance evaluations validate the architecture’s superiority over traditional reversible logic circuits, demonstrating significant improvements in power efficiency and computational throughput. By leveraging quantum-inspired reversible gates and parallelism, this design lays a foundation for next-generation low-power, scalable circuits suitable for quantum computing, nanotechnology, and energy-constrained environments.
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ISSN:2661-8907
2662-995X
2661-8907
DOI:10.1007/s42979-025-04062-6