Potharaju, V. S., & Saminadan, V. (2025). Design and Analysis of Low Power Reversible Majority Logic-Based Adder/Subtractor Circuits with Parallel Computing Optimization. SN computer science, 6(6), 645. https://doi.org/10.1007/s42979-025-04062-6
Citácia podle Chicago (17th ed.)Potharaju, Vidya Sagar, a V. Saminadan. "Design and Analysis of Low Power Reversible Majority Logic-Based Adder/Subtractor Circuits with Parallel Computing Optimization." SN Computer Science 6, no. 6 (2025): 645. https://doi.org/10.1007/s42979-025-04062-6.
Citácia podľa MLA (8th ed.)Potharaju, Vidya Sagar, a V. Saminadan. "Design and Analysis of Low Power Reversible Majority Logic-Based Adder/Subtractor Circuits with Parallel Computing Optimization." SN Computer Science, vol. 6, no. 6, 2025, p. 645, https://doi.org/10.1007/s42979-025-04062-6.