A High-Throughput Constructive Interference Precoder for 16 × MU-MIMO Systems

In a multiuser multiple-input multiple-output (MU-MIMO) downlink system, users are susceptible to interuser interference (IUI) because of data being simultaneously transmitted over the same time-frequency resources. Conventionally, precoding algorithms aim to eliminate the IUI. However, constructive...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems Vol. 32; no. 10; pp. 1878 - 1888
Main Authors: Lin, Yu-Cheng, Chiou, Ren-Hao, Yang, Chia-Hsiang
Format: Journal Article
Language:English
Published: New York IEEE 01.10.2024
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:
Algorithms
Bit error rate
Constructive interference (CI)
Design optimization
Downlink
downlink precoding
Interference
Iterative algorithms
MIMO communication
multiuser multiple-input multiple-output (MU-MIMO)
Optimization
Precoding
Quadrature amplitude modulation
Resource allocation
Symbols
Time multiplexing
Vectors
VLSI architecture
ISSN:1063-8210, 1557-9999
Online Access:Get full text
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Summary:In a multiuser multiple-input multiple-output (MU-MIMO) downlink system, users are susceptible to interuser interference (IUI) because of data being simultaneously transmitted over the same time-frequency resources. Conventionally, precoding algorithms aim to eliminate the IUI. However, constructive interference (CI) precoding can achieve better error performance by exploiting the IUI. This article presents a high-throughput CI precoder. Design optimization across the algorithm and the architecture layers is conducted, reducing the complexity for multiplications by 81.6%. As the number of iterations for convergence varies, dynamic resource allocation is utilized to support each modulation mode with maximized utilization: time-multiplexing for the 4-QAM mode and parallel-processing for the 16-QAM mode. The proposed symbol updater also allows more efficient scheduling. As a proof of concept, a CI precoder chip that supports up to <inline-formula> <tex-math notation="LaTeX">16 \times </tex-math></inline-formula> MU-MIMO systems is designed based in a 40-nm CMOS technology. The performance gains at a bit error rate (BER) <inline-formula> <tex-math notation="LaTeX">= 10^{-4} </tex-math></inline-formula> are 10.7 and 12.5 dB for 4-QAM and 16-QAM, respectively, compared with conventional regularized zero-forcing (RZF) schemes. The precoder delivers a maximum throughput of 3.2 Gb/s at a clock frequency of 200 MHz for the <inline-formula> <tex-math notation="LaTeX">16 \times </tex-math></inline-formula> MU-MIMO configuration.
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ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2024.3423341