A High-Throughput Constructive Interference Precoder for 16 × MU-MIMO Systems

In a multiuser multiple-input multiple-output (MU-MIMO) downlink system, users are susceptible to interuser interference (IUI) because of data being simultaneously transmitted over the same time-frequency resources. Conventionally, precoding algorithms aim to eliminate the IUI. However, constructive...

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Published in:IEEE transactions on very large scale integration (VLSI) systems Vol. 32; no. 10; pp. 1878 - 1888
Main Authors: Lin, Yu-Cheng, Chiou, Ren-Hao, Yang, Chia-Hsiang
Format: Journal Article
Language:English
Published: New York IEEE 01.10.2024
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:
Algorithms
Bit error rate
Constructive interference (CI)
Design optimization
Downlink
downlink precoding
Interference
Iterative algorithms
MIMO communication
multiuser multiple-input multiple-output (MU-MIMO)
Optimization
Precoding
Quadrature amplitude modulation
Resource allocation
Symbols
Time multiplexing
Vectors
VLSI architecture
ISSN:1063-8210, 1557-9999
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Abstract In a multiuser multiple-input multiple-output (MU-MIMO) downlink system, users are susceptible to interuser interference (IUI) because of data being simultaneously transmitted over the same time-frequency resources. Conventionally, precoding algorithms aim to eliminate the IUI. However, constructive interference (CI) precoding can achieve better error performance by exploiting the IUI. This article presents a high-throughput CI precoder. Design optimization across the algorithm and the architecture layers is conducted, reducing the complexity for multiplications by 81.6%. As the number of iterations for convergence varies, dynamic resource allocation is utilized to support each modulation mode with maximized utilization: time-multiplexing for the 4-QAM mode and parallel-processing for the 16-QAM mode. The proposed symbol updater also allows more efficient scheduling. As a proof of concept, a CI precoder chip that supports up to <inline-formula> <tex-math notation="LaTeX">16 \times </tex-math></inline-formula> MU-MIMO systems is designed based in a 40-nm CMOS technology. The performance gains at a bit error rate (BER) <inline-formula> <tex-math notation="LaTeX">= 10^{-4} </tex-math></inline-formula> are 10.7 and 12.5 dB for 4-QAM and 16-QAM, respectively, compared with conventional regularized zero-forcing (RZF) schemes. The precoder delivers a maximum throughput of 3.2 Gb/s at a clock frequency of 200 MHz for the <inline-formula> <tex-math notation="LaTeX">16 \times </tex-math></inline-formula> MU-MIMO configuration.
AbstractList In a multiuser multiple-input multiple-output (MU-MIMO) downlink system, users are susceptible to interuser interference (IUI) because of data being simultaneously transmitted over the same time-frequency resources. Conventionally, precoding algorithms aim to eliminate the IUI. However, constructive interference (CI) precoding can achieve better error performance by exploiting the IUI. This article presents a high-throughput CI precoder. Design optimization across the algorithm and the architecture layers is conducted, reducing the complexity for multiplications by 81.6%. As the number of iterations for convergence varies, dynamic resource allocation is utilized to support each modulation mode with maximized utilization: time-multiplexing for the 4-QAM mode and parallel-processing for the 16-QAM mode. The proposed symbol updater also allows more efficient scheduling. As a proof of concept, a CI precoder chip that supports up to <inline-formula> <tex-math notation="LaTeX">16 \times </tex-math></inline-formula> MU-MIMO systems is designed based in a 40-nm CMOS technology. The performance gains at a bit error rate (BER) <inline-formula> <tex-math notation="LaTeX">= 10^{-4} </tex-math></inline-formula> are 10.7 and 12.5 dB for 4-QAM and 16-QAM, respectively, compared with conventional regularized zero-forcing (RZF) schemes. The precoder delivers a maximum throughput of 3.2 Gb/s at a clock frequency of 200 MHz for the <inline-formula> <tex-math notation="LaTeX">16 \times </tex-math></inline-formula> MU-MIMO configuration.
In a multiuser multiple-input multiple-output (MU-MIMO) downlink system, users are susceptible to interuser interference (IUI) because of data being simultaneously transmitted over the same time-frequency resources. Conventionally, precoding algorithms aim to eliminate the IUI. However, constructive interference (CI) precoding can achieve better error performance by exploiting the IUI. This article presents a high-throughput CI precoder. Design optimization across the algorithm and the architecture layers is conducted, reducing the complexity for multiplications by 81.6%. As the number of iterations for convergence varies, dynamic resource allocation is utilized to support each modulation mode with maximized utilization: time-multiplexing for the 4-QAM mode and parallel-processing for the 16-QAM mode. The proposed symbol updater also allows more efficient scheduling. As a proof of concept, a CI precoder chip that supports up to [Formula Omitted] MU-MIMO systems is designed based in a 40-nm CMOS technology. The performance gains at a bit error rate (BER) [Formula Omitted] are 10.7 and 12.5 dB for 4-QAM and 16-QAM, respectively, compared with conventional regularized zero-forcing (RZF) schemes. The precoder delivers a maximum throughput of 3.2 Gb/s at a clock frequency of 200 MHz for the [Formula Omitted] MU-MIMO configuration.
Author Chiou, Ren-Hao
Lin, Yu-Cheng
Yang, Chia-Hsiang
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Cites_doi 10.1109/TCOMM.2020.3031616
10.1109/TSP.2014.2362880
10.1109/TCSI.2019.2899211
10.1109/TCSI.2016.2604380
10.1109/TSP.2003.821110
10.1525/9780520411586-036
10.1109/TCOMM.2004.840638
10.1109/TWC.2017.2712604
10.1109/TIT.1983.1056659
10.1109/TSP.2012.2218812
10.1109/TCSII.2013.2291074
10.1007/s10107-002-0339-5
10.1109/TWC.2018.2869382
10.1109/TCSI.2019.2893274
10.1109/TWC.2018.2876229
10.1109/ICC.2007.470
10.1109/TWC.2018.2860011
10.1109/TIT.2003.814483
10.1109/MCOM.2004.1341262
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References ref13
ref12
ref23
ref15
Krylov (ref22) 1972; 1
ref11
ref10
ref21
Nocedal (ref14) 2006
Nutini (ref18)
ref2
ref1
ref17
ref16
ref19
ref8
ref7
ref9
ref4
ref3
Li (ref20) 2020
ref6
ref5
References_xml – ident: ref8
  doi: 10.1109/TCOMM.2020.3031616
– ident: ref16
  doi: 10.1109/TSP.2014.2362880
– ident: ref13
  doi: 10.1109/TCSI.2019.2899211
– ident: ref11
  doi: 10.1109/TCSI.2016.2604380
– ident: ref15
  doi: 10.1109/TSP.2003.821110
– volume: 1
  start-page: 168
  year: 1972
  ident: ref22
  publication-title: Computational Methods of Higher Mathematics
– ident: ref17
  doi: 10.1525/9780520411586-036
– year: 2020
  ident: ref20
  article-title: Symbol-level precoding made practical for multi-level modulations via block-level rescaling
  publication-title: arXiv:2006.15245
– ident: ref4
  doi: 10.1109/TCOMM.2004.840638
– ident: ref10
  doi: 10.1109/TWC.2017.2712604
– ident: ref2
  doi: 10.1109/TIT.1983.1056659
– start-page: 467
  volume-title: Numerical Optimization
  year: 2006
  ident: ref14
– ident: ref19
  doi: 10.1109/TSP.2012.2218812
– ident: ref23
  doi: 10.1109/TCSII.2013.2291074
– ident: ref6
  doi: 10.1007/s10107-002-0339-5
– ident: ref7
  doi: 10.1109/TWC.2018.2869382
– ident: ref12
  doi: 10.1109/TCSI.2019.2893274
– ident: ref9
  doi: 10.1109/TWC.2018.2876229
– ident: ref5
  doi: 10.1109/ICC.2007.470
– ident: ref21
  doi: 10.1109/TWC.2018.2860011
– ident: ref1
  doi: 10.1109/TIT.2003.814483
– start-page: 1632
  volume-title: Proc. 32nd Int. Conf. Mach. Learn.
  ident: ref18
  article-title: Coordinate descent converges faster with the Gauss–Southwell rule than random selection
– ident: ref3
  doi: 10.1109/MCOM.2004.1341262
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SubjectTerms Algorithms
Bit error rate
Constructive interference (CI)
Design optimization
Downlink
downlink precoding
Interference
Iterative algorithms
MIMO communication
multiuser multiple-input multiple-output (MU-MIMO)
Optimization
Precoding
Quadrature amplitude modulation
Resource allocation
Symbols
Time multiplexing
Vectors
VLSI architecture
Title A High-Throughput Constructive Interference Precoder for 16 × MU-MIMO Systems
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