Implementación del algoritmo Threefish-256 en hardware reconfigurable

This article  presents  both  the  description and  results  of  the Threefish  cryptographic  algorithm hardware  implementation  for  encryption  process. The implementation of the algorithm was performed by using the iterative round architecture on the FPGA (Field Programmable Gate Array) Virtex-...

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Bibliographic Details
Published in:Iteckne Vol. 11; no. 2; pp. 149 - 156
Main Authors: Nieto-Ramírez, Nathaly, Nieto-Londoño, Rubén Darío
Format: Journal Article
Language:English
Published: Universidad Santo Tomás 31.12.2014
Subjects:
criptografía, diseño síncrono, fpga, threefish, vhdl
ISSN:1692-1798, 2339-3483
Online Access:Get full text
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Description
Summary:This article  presents  both  the  description and  results  of  the Threefish  cryptographic  algorithm hardware  implementation  for  encryption  process. The implementation of the algorithm was performed by using the iterative round architecture on the FPGA (Field Programmable Gate Array) Virtex-5 present in the development system XUPV5-LX110T. Place and route results show that the design Threefish-256 iterative round has a throughput of 551Mbps.
ISSN:1692-1798
2339-3483
DOI:10.15332/iteckne.v11i2.725