RelOps: Reliability Optimization in Standard Cells across PVT Variations in FinFET Digital Circuits

FinFET, now firmly established in leading VLSI industries for their superior performance, exhibit heightened aging susceptibility that poses significant reliability challenges. The aggressive scaling of technology nodes has further compromised circuit reliability in recent years, highlighting the ne...

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Vydáno v:IEEE transactions on computer-aided design of integrated circuits and systems s. 1
Hlavní autoři: Akhtar, Mohammad Rehan, Goswami, Ritwik Basyas, Abbas, Zia
Médium: Journal Article
Jazyk:angličtina
Vydáno: IEEE 2025
Témata:
Aging
Delays
FinFET
FinFETs
Integrated circuit modeling
Machine Learning
Negative bias temperature instability
Optimization
Optimization Algorithm
PDP
Performance evaluation
PVT
Reliability
Thermal variables control
ISSN:0278-0070, 1937-4151
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Shrnutí:FinFET, now firmly established in leading VLSI industries for their superior performance, exhibit heightened aging susceptibility that poses significant reliability challenges. The aggressive scaling of technology nodes has further compromised circuit reliability in recent years, highlighting the need for effective aging mitigation techniques. Recent advancements in the miniaturization of nanoscale technology have demonstrated the potential of optimizing performance parameters in standard cells using machine learning models and optimization algorithms through device sizing modifications. Building on this progress, we propose a methodology for optimizing performance parameters in 16nm high-performance (HP) FinFET for the first time. The approach leverages a multi-objective optimization algorithm framework to mitigate aging impacts across PVT variations while addressing NBTI and HCI effects by optimally adjusting FinFET design parameters, including channel length (lg), width (tfin), and height (hfin). With SPICE simulations, time-series datasets were generated to train machine learning models that achieved an R2 score exceeding 0.99 and a mean absolute percentage error below 1% across standard cells. Our approach yields a significant simulation speedup and a reduction in simulation workload compared to traditional SPICE simulations. Using the proposed optimization algorithm framework, we improved the power-delay product (PDP) by up to 36.97% under non-aging conditions and 34.94% with aging considered with respect to the nominal dimension at the fresh year, demonstrating significant performance gains for FinFET-based standard cells. The experimental results on 12 distinct complex cells validate the aging mitigation across years.
ISSN:0278-0070
1937-4151
DOI:10.1109/TCAD.2025.3593207