Design and Implementation of DynamicLoad Balancing Algorithms for Rollback Reductionin Optimistic PDES
In an optimistic parallel simulation, logical processes (Ips) proceed with their computation without any constraints. However, if the computing requirements of different lps are not balanced or if the processors are not homogeneous, some lps may lag behind in simulation time while others surge forwa...
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| Vydáno v: | VLSI design (Yverdon, Switzerland) Ročník 9; číslo 3; s. 271 - 290 |
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| Hlavní autoři: | , |
| Médium: | Journal Article |
| Jazyk: | angličtina |
| Vydáno: |
01.01.1999
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| ISSN: | 1065-514X, 1563-5171 |
| On-line přístup: | Získat plný text |
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| Shrnutí: | In an optimistic parallel simulation, logical processes (Ips) proceed with their
computation without any constraints. However, if the computing requirements of
different lps are not balanced or if the processors are not homogeneous, some lps may
lag behind in simulation time while others surge forward. In other words, if the
simulation clocks of different lps are not progressing at the same rate, cascading
rollbacks may occur nullifying the potential benefit of an optimistic parallel discrete
event simulation (PDES). Hence it is necessary to balance the computational load on
different lps in such a way that their local simulation clocks advance almost at the same
rate. In this paper, we propose two algorithms for dynamic load balancing which reduce
the number of rollbacks in an optimistic PDES system. Our first algorithm is based on
the load transfer mechanism between lps; while the second algorithm, based on the
principle of evolutionary strategy, migrates logical processes between several pairs of
physical processors. We have implemented both of these algorithms on a cluster of
heterogeneous workstations and studied their performance. The experimental results
show that the algorithm based on the load transfer is effective when the grain size is
greater than 10 milliseconds. The algorithm based on the process migration yields good
performance only for grain sizes of 20 milliseconds or larger. In both of these cases the
speed up ranges mostly between and 2 using four processors. |
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| ISSN: | 1065-514X 1563-5171 |
| DOI: | 10.1155/1999/64750 |