47‐4: A Novel Demura Compensation Data Compression Algorithm based on JPEG‐LS

JPEG‐LS is a lossless/near‐lossless image compression algorithm based on context modeling, which has the advantages of easy implementation, low resource consumption and high compression rate. It is widely used in the compression field of continuous‐tone still images. However, single image compressio...

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Veröffentlicht in:SID International Symposium Digest of technical papers Jg. 55; H. 1; S. 634 - 637
Hauptverfasser: Chen, Lin, Wang, Shuaizhao, Guo, Xingling, Tan, Xiaoping, Huang, Jiting, Ge, Mingwei, Zhu, Xiujian
Format: Journal Article
Sprache:Englisch
Veröffentlicht: Campbell Wiley Subscription Services, Inc 01.06.2024
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ISSN:0097-966X, 2168-0159
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Zusammenfassung:JPEG‐LS is a lossless/near‐lossless image compression algorithm based on context modeling, which has the advantages of easy implementation, low resource consumption and high compression rate. It is widely used in the compression field of continuous‐tone still images. However, single image compression has significant latency and high hardware resource consumption issues, as the JPEG‐LS algorithm requires pixel by pixel prediction and real‐time context updates during the compression process, which is not conducive to algorithm IP implementation. Based on Demura compensation data compression requirements, this article has made changes to the pixel prediction method of the JPEG‐LS algorithm and delayed the update of the context to solve the compression latency and resource consumption issues. After algorithm optimization (NJPEGLS), the linebuffer resource occupation was reduced by 8/9, the clock frequency reached above 140 MHz, and the comprehensive compression rate loss was within 4.5%, meeting the demand for Demura compensation data compression/decompression. In this paper, we also conducted statistics and analysis on the distribution of values, and found that the distribution of values was very regular, and we propose an adaptive value scheme (KNJPEG‐LS) to further simplify the hardware circuit.
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ISSN:0097-966X
2168-0159
DOI:10.1002/sdtp.17604