Clock gating for power optimization in ASIC design cycle theory & practice

In this tutorial we present a comprehensive analysis of the available clock gate (CG) optimization approaches with re-cent innovations available in EDA tools as they have developed in time. Based on these approaches, we propose an integrated and additive design methodology spanning the backend desig...

Celý popis

Uložené v:

Podrobná bibliografia
Vydané v:	Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) s. 307 - 308
Hlavní autori:	S, Jairam, Rao, Madhusudan, Srinivas, Jithendra, Vishwanath, Parimala, H, Udayakumar, Rao, Jagdish
Médium:	Konferenčný príspevok..
Jazyk:	English
Vydavateľské údaje:	New York, NY, USA ACM 11.08.2008 IEEE
Edícia:	ACM Conferences
Predmet:	Application specific integrated circuits ASIC Character generation Clocks Design methodology Design optimization Dynamic voltage scaling Electronic design automation and methodology Hardware > Electronic design automation > Hardware description languages and compilation Hardware > Electronic design automation > Logic synthesis > Circuit optimization History Logic low power optimization RTL SoC Technological innovation low power ASIC RTL optimization SoC
ISBN:	9781605581095, 1605581097, 9781424486342, 1424486343
On-line prístup:	Získať plný text
Tagy:	Pridať tag Žiadne tagy, Buďte prvý, kto otaguje tento záznam!

Buďte prvý, kto okomentuje tento záznam!