FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis

We propose strategies to achieve a high-throughput FPGA architecture for quasi-cyclic low-density parity-check codes based on circulant-1 identity matrix construction. By splitting the node processing operation in the min-sum approximation algorithm, we achieve pipelining in the layered decoding sch...

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Bibliographic Details

Published in:	International Journal of Reconfigurable Computing Vol. 2017; no. 2017; pp. 1 - 23-004
Main Authors:	Aziz, Ahsan, Ly, Tai, Kee, Hojin, Mhaske, Swapnil, Spasojevic, Predrag
Format:	Journal Article
Language:	English
Published:	Cairo, Egypt Hindawi Limiteds 01.01.2017 Hindawi Publishing Corporation Hindawi John Wiley & Sons, Inc Wiley
Subjects:	Algorithms Automation Design Designers Digital integrated circuits Digital signal processors Error-correcting codes Low density parity check codes Rapid prototyping Research methodology Signal processing Subject specialists Wi-Fi Wireless local area networks (Computer networks)
ISSN:	1687-7195, 1687-7209
Online Access:	Get full text
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