FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis

We propose strategies to achieve a high-throughput FPGA architecture for quasi-cyclic low-density parity-check codes based on circulant-1 identity matrix construction. By splitting the node processing operation in the min-sum approximation algorithm, we achieve pipelining in the layered decoding sch...

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Vydáno v:International Journal of Reconfigurable Computing Ročník 2017; číslo 2017; s. 1 - 23-004
Hlavní autoři: Aziz, Ahsan, Ly, Tai, Kee, Hojin, Mhaske, Swapnil, Spasojevic, Predrag
Médium: Journal Article
Jazyk:angličtina
Vydáno: Cairo, Egypt Hindawi Limiteds 01.01.2017
Hindawi Publishing Corporation
Hindawi
John Wiley & Sons, Inc
Wiley
Témata:
Algorithms
Automation
Design
Designers
Digital integrated circuits
Digital signal processors
Error-correcting codes
Low density parity check codes
Rapid prototyping
Research methodology
Signal processing
Subject specialists
Wi-Fi
Wireless local area networks (Computer networks)
ISSN:1687-7195, 1687-7209
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Shrnutí:We propose strategies to achieve a high-throughput FPGA architecture for quasi-cyclic low-density parity-check codes based on circulant-1 identity matrix construction. By splitting the node processing operation in the min-sum approximation algorithm, we achieve pipelining in the layered decoding schedule without utilizing additional hardware resources. High-level synthesis compilation is used to design and develop the architecture on the FPGA hardware platform. To validate this architecture, an IEEE 802.11n compliant 608 Mb/s decoder is implemented on the Xilinx Kintex-7 FPGA using the LabVIEW FPGA Compiler in the LabVIEW Communication System Design Suite. Architecture scalability was leveraged to accomplish a 2.48 Gb/s decoder on a single Xilinx Kintex-7 FPGA. Further, we present rapidly prototyped experimentation of an IEEE 802.16 compliant hybrid automatic repeat request system based on the efficient decoder architecture developed. In spite of the mixed nature of data processing—digital signal processing and finite-state machines—LabVIEW FPGA Compiler significantly reduced time to explore the system parameter space and to optimize in terms of error performance and resource utilization. A 4x improvement in the system throughput, relative to a CPU-based implementation, was achieved to measure the error-rate performance of the system over large, realistic data sets using accelerated, in-hardware simulation.
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ISSN:1687-7195
1687-7209
DOI:10.1155/2017/3689308