An Impulse-C Hardware Accelerator for Packet Classification Based on Fine/Coarse Grain Optimization
Current software-based packet classification algorithms exhibit relatively poor performance, prompting many researchers to concentrate on novel frameworks and architectures that employ both hardware and software components. The Packet Classification with Incremental Update (PCIU) algorithm, Ahmed et...
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| Vydáno v: | International Journal of Reconfigurable Computing Ročník 2013; číslo 2013; s. 3 - 25 |
|---|---|
| Hlavní autoři: | , , , |
| Médium: | Journal Article |
| Jazyk: | angličtina |
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Cairo, Egypt
Hindawi Limiteds
01.01.2013
Hindawi Puplishing Corporation Hindawi Publishing Corporation John Wiley & Sons, Inc Wiley |
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| ISSN: | 1687-7195, 1687-7209 |
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| Abstract | Current software-based packet classification algorithms exhibit relatively poor performance, prompting many researchers to concentrate on novel frameworks and architectures that employ both hardware and software components. The Packet Classification with Incremental Update (PCIU) algorithm, Ahmed et al. (2010), is a novel and efficient packet classification algorithm with a unique incremental update capability that demonstrated excellent results and was shown to be scalable for many different tasks and clients. While a pure software implementation can generate powerful results on a server machine, an embedded solution may be more desirable for some applications and clients. Embedded, specialized hardware accelerator based solutions are typically much more efficient in speed, cost, and size than solutions that are implemented on general-purpose processor systems. This paper seeks to explore the design space of translating the PCIU algorithm into hardware by utilizing several optimization techniques, ranging from fine grain to coarse grain and parallel coarse grain approaches. The paper presents a detailed implementation of a hardware accelerator of the PCIU based on an Electronic System Level (ESL) approach. Results obtained indicate that the hardware accelerator achieves on average 27x speedup over a state-of-the-art Xeon processor. |
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| AbstractList | Current software-based packet classification algorithms exhibit relatively poor performance, prompting many researchers to concentrate on novel frameworks and architectures that employ both hardware and software components. The Packet Classification with Incremental Update (PCIU) algorithm, Ahmed et al. (2010), is a novel and efficient packet classification algorithm with a unique incremental update capability that demonstrated excellent results and was shown to be scalable for many different tasks and clients. While a pure software implementation can generate powerful results on a server machine, an embedded solution may be more desirable for some applications and clients. Embedded, specialized hardware accelerator based solutions are typically much more efficient in speed, cost, and size than solutions that are implemented on general-purpose processor systems. This paper seeks to explore the design space of translating the PCIU algorithm into hardware by utilizing several optimization techniques, ranging from fine grain to coarse grain and parallel coarse grain approaches. The paper presents a detailed implementation of a hardware accelerator of the PCIU based on an Electronic System Level (ESL) approach. Results obtained indicate that the hardware accelerator achieves on average 27x speedup over a state-of-the-art Xeon processor. |
| Audience | Academic |
| Author | R. Collier G. Grewal O. Ahmed S. Areibi |
| Author_xml | – sequence: 1 fullname: Grewal, G. – sequence: 2 fullname: Areibi, Shawki – sequence: 3 fullname: Ahmed, O. – sequence: 4 fullname: Collier, R. |
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| Cites_doi | 10.1109/TNET.2010.2061864 10.1155/2013/681894 10.1145/1108956.1108958 10.1155/2011/648483 10.1109/TVLSI.2011.2162112 10.1109/TCAD.2011.2110592 |
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| Contributor | Collier, R Areibi, Shawki Grewal, G Ahmed, O |
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| Copyright | Copyright © 2013 O. Ahmed et al. COPYRIGHT 2013 John Wiley & Sons, Inc. Copyright © 2013 O. Ahmed et al. O. Ahmed et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. |
| Copyright_xml | – notice: Copyright © 2013 O. Ahmed et al. – notice: COPYRIGHT 2013 John Wiley & Sons, Inc. – notice: Copyright © 2013 O. Ahmed et al. O. Ahmed et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. |
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| References | (7) 2011; 30 RG Handel-C language reference manual 2005 Europe Celoxica Gupta P. McKeown N. Packet classification on multiple fields Proceedings of the Conference on Applications, Technologies, Architectures, and Protocols for Computer Communication 1999 New York, NY, USA ACM 147 160 Chang Y.-K. Lee C.-I. Su C.-C. Multi-field range encoding for packet classification in TCAM Proceedings of the 30th IEEE International Conference on Computer Communications (INFOCOM '11) April 2011 Shanghai, China 196 200 2-s2.0-79960873537 10.1109/INFCOM.2011.5935001 Pellerin D. Thibault S. Practical FPGA Programming in C 2005 1st Upper Saddle River, NJ, USA Prentice Hall Press Ahmed O. Areibi S. Fayek D. PCIU: an efficient packet classification algorithm with an incremental update capability Proceedings of the International Symposium on Performance Evaluation of Computer and Telecommunication Systems (SPECTS '10) July 2010 Ottawa, Canada 81 88 2-s2.0-78649232410 Chang Y.-K. Lin Y.-S. Su C.-C. A high-speed and memory efficient pipeline architecture for packet classification Proceedings of the 18th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM '10) May 2010 usa 215 218 2-s2.0-77954252458 10.1109/FCCM.2010.40 (21) 2013; 2013 Le H. Jiang W. Prasanna V. K. Scalable high-throughput sram-based architecture for ip-lookup using FPGA Proceedings of the International Conference on Field Programmable Logic and Applications (FPL '08) September 2008 137 142 2-s2.0-54949110989 10.1109/FPL.2008.4629921 (17) 2011; 2011 (12) 2011; 19 Nikitakis A. Papaefstathiou I. A memory-efficient FPGA-based classification engine Proceedings of the 16th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '08) April 2008 53 62 2-s2.0-60349092688 10.1109/FCCM.2008.29 IC Impulse accelerated technologies 2011, http://www.impulseaccelerated.com (22) 2005; 37 Ahmed O. Areibi S. Software implementation of the PCIU algorithm 2013, http://deimos.eos.uoguelph.ca/sareibi/PUBLICATIONS_dr/software_code_dr/PCIU_Software.html (20) 2011 Taylor D. E. Turner J. S. ClassBench: a packet classification benchmark Proceedings of the 24th IEEE International Conference on Computer Communications (INFOCOM '05) March 2005 Miami, Fla, USA 2068 2079 2-s2.0-25844521204 Bobda C. Introduction to Reconfigurable Computing: Architectures, Algorithms and Applications 2007 Dordrecht, The Netherlands Springer Antichi G. Di Pietro A. Giordano S. Procissi G. Ficara D. Vitucci F. On the use of compressed DFAs for packet classification Proceedings of the 15th IEEE International Workshop on Computer Aided Modeling, Analysis and Design of Communication Links and Networks (CAMAD '10) December 2010 21 25 2-s2.0-79951488654 10.1109/CAMAD.2010.5686971 Lim H. Mun J. H. High-speed packet classification using binary search on length Proceedings of the 3rd ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS '07) December 2007 New York, NY, USA 137 144 2-s2.0-58049131273 10.1145/1323548.1323572 Calypto Catapult C synthesis 2012, http://www.calypto.com Papaefstathiou I. Papaefstathiou V. Memory-efficient 5D packet classification at 40 Gbps Proceedings of the 26th IEEE International Conference on Computer Communications (INFOCOM '07) May 2007 Anchorage , Alaska , USA 1370 1378 2-s2.0-34548300051 10.1109/INFCOM.2007.162 Xilinx C-based design: high level synthesis with vivado hls 2013, http://www.xilinx.com/training/dsp/high-level-synthesis-with-vivado-hls.htm Jedhe G. S. Ramamoorthy A. Varghese K. A scalable high throughput firewall in FPGA Proceedings of the 16th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '08) April 2008 Palo Alto, Calif, USA 43 52 2-s2.0-60349110115 10.1109/FCCM.2008.31 22 12 17 7 (23) 2005 (6) 2007 20 21 |
| References_xml | – reference: Gupta P. McKeown N. Packet classification on multiple fields Proceedings of the Conference on Applications, Technologies, Architectures, and Protocols for Computer Communication 1999 New York, NY, USA ACM 147 160 – reference: Le H. Jiang W. Prasanna V. K. Scalable high-throughput sram-based architecture for ip-lookup using FPGA Proceedings of the International Conference on Field Programmable Logic and Applications (FPL '08) September 2008 137 142 2-s2.0-54949110989 10.1109/FPL.2008.4629921 – reference: Chang Y.-K. Lee C.-I. Su C.-C. Multi-field range encoding for packet classification in TCAM Proceedings of the 30th IEEE International Conference on Computer Communications (INFOCOM '11) April 2011 Shanghai, China 196 200 2-s2.0-79960873537 10.1109/INFCOM.2011.5935001 – reference: Papaefstathiou I. Papaefstathiou V. Memory-efficient 5D packet classification at 40 Gbps Proceedings of the 26th IEEE International Conference on Computer Communications (INFOCOM '07) May 2007 Anchorage , Alaska , USA 1370 1378 2-s2.0-34548300051 10.1109/INFCOM.2007.162 – volume: 2013 year: 2013 end-page: 33 ident: 21 article-title: Hardware accelerators targeting a novel group based packet classification algorithm – volume: 37 start-page: 238 issue: 3 year: 2005 end-page: 275 ident: 22 article-title: Survey and taxonomy of packet classification techniques – reference: RG Handel-C language reference manual 2005 Europe Celoxica – reference: IC Impulse accelerated technologies 2011, http://www.impulseaccelerated.com/ – reference: Lim H. Mun J. H. High-speed packet classification using binary search on length Proceedings of the 3rd ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS '07) December 2007 New York, NY, USA 137 144 2-s2.0-58049131273 10.1145/1323548.1323572 – reference: Bobda C. Introduction to Reconfigurable Computing: Architectures, Algorithms and Applications 2007 Dordrecht, The Netherlands Springer – reference: Jedhe G. S. Ramamoorthy A. Varghese K. A scalable high throughput firewall in FPGA Proceedings of the 16th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '08) April 2008 Palo Alto, Calif, USA 43 52 2-s2.0-60349110115 10.1109/FCCM.2008.31 – start-page: 1668 issue: 99 year: 2011 end-page: 1680 ident: 20 article-title: Scalable packet classification on FPGA – reference: Antichi G. Di Pietro A. Giordano S. Procissi G. Ficara D. Vitucci F. On the use of compressed DFAs for packet classification Proceedings of the 15th IEEE International Workshop on Computer Aided Modeling, Analysis and Design of Communication Links and Networks (CAMAD '10) December 2010 21 25 2-s2.0-79951488654 10.1109/CAMAD.2010.5686971 – volume: 30 start-page: 473 issue: 4 year: 2011 end-page: 491 ident: 7 article-title: High-level synthesis for FPGAs: from prototyping to deployment – reference: Chang Y.-K. Lin Y.-S. Su C.-C. A high-speed and memory efficient pipeline architecture for packet classification Proceedings of the 18th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM '10) May 2010 usa 215 218 2-s2.0-77954252458 10.1109/FCCM.2010.40 – reference: Pellerin D. Thibault S. Practical FPGA Programming in C 2005 1st Upper Saddle River, NJ, USA Prentice Hall Press – reference: Xilinx C-based design: high level synthesis with vivado hls 2013, http://www.xilinx.com/training/dsp/high-level-synthesis-with-vivado-hls.htm – reference: Taylor D. E. Turner J. S. ClassBench: a packet classification benchmark Proceedings of the 24th IEEE International Conference on Computer Communications (INFOCOM '05) March 2005 Miami, Fla, USA 2068 2079 2-s2.0-25844521204 – volume: 19 start-page: 237 issue: 1 year: 2011 end-page: 250 ident: 12 article-title: Topological transformation approaches to TCAM-Based packet classification – reference: Ahmed O. Areibi S. Fayek D. PCIU: an efficient packet classification algorithm with an incremental update capability Proceedings of the International Symposium on Performance Evaluation of Computer and Telecommunication Systems (SPECTS '10) July 2010 Ottawa, Canada 81 88 2-s2.0-78649232410 – reference: Ahmed O. Areibi S. Software implementation of the PCIU algorithm 2013, http://deimos.eos.uoguelph.ca/sareibi/PUBLICATIONS_dr/software_code_dr/PCIU_Software.html – reference: Nikitakis A. Papaefstathiou I. A memory-efficient FPGA-based classification engine Proceedings of the 16th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '08) April 2008 53 62 2-s2.0-60349092688 10.1109/FCCM.2008.29 – reference: Calypto Catapult C synthesis 2012, http://www.calypto.com – volume: 2011 year: 2011 end-page: 21 ident: 17 article-title: PCIU: Hardware implementations of an efficient packet classification algorithm with an incremental update capability – year: 2007 ident: 6 – ident: 12 doi: 10.1109/TNET.2010.2061864 – ident: 21 doi: 10.1155/2013/681894 – ident: 22 doi: 10.1145/1108956.1108958 – ident: 17 doi: 10.1155/2011/648483 – ident: 20 doi: 10.1109/TVLSI.2011.2162112 – year: 2005 ident: 23 – ident: 7 doi: 10.1109/TCAD.2011.2110592 |
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| Title | An Impulse-C Hardware Accelerator for Packet Classification Based on Fine/Coarse Grain Optimization |
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