An Impulse-C Hardware Accelerator for Packet Classification Based on Fine/Coarse Grain Optimization

Current software-based packet classification algorithms exhibit relatively poor performance, prompting many researchers to concentrate on novel frameworks and architectures that employ both hardware and software components. The Packet Classification with Incremental Update (PCIU) algorithm, Ahmed et...

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Vydané v:International Journal of Reconfigurable Computing Ročník 2013; číslo 2013; s. 3 - 25
Hlavní autori: Grewal, G., Areibi, Shawki, Ahmed, O., Collier, R.
Médium: Journal Article
Jazyk:English
Vydavateľské údaje: Cairo, Egypt Hindawi Limiteds 01.01.2013
Hindawi Puplishing Corporation
Hindawi Publishing Corporation
John Wiley & Sons, Inc
Wiley
Predmet:
Algorithms
Analysis
Computer software
Design
Field programmable gate arrays
Microprocessors
Network switching
Product introduction
ISSN:1687-7195, 1687-7209
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Shrnutí:Current software-based packet classification algorithms exhibit relatively poor performance, prompting many researchers to concentrate on novel frameworks and architectures that employ both hardware and software components. The Packet Classification with Incremental Update (PCIU) algorithm, Ahmed et al. (2010), is a novel and efficient packet classification algorithm with a unique incremental update capability that demonstrated excellent results and was shown to be scalable for many different tasks and clients. While a pure software implementation can generate powerful results on a server machine, an embedded solution may be more desirable for some applications and clients. Embedded, specialized hardware accelerator based solutions are typically much more efficient in speed, cost, and size than solutions that are implemented on general-purpose processor systems. This paper seeks to explore the design space of translating the PCIU algorithm into hardware by utilizing several optimization techniques, ranging from fine grain to coarse grain and parallel coarse grain approaches. The paper presents a detailed implementation of a hardware accelerator of the PCIU based on an Electronic System Level (ESL) approach. Results obtained indicate that the hardware accelerator achieves on average 27x speedup over a state-of-the-art Xeon processor.
Bibliografia:ObjectType-Article-1
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ISSN:1687-7195
1687-7209
DOI:10.1155/2013/130765