MBus: An ultra-low power interconnect bus for next generation nanopower systems

As we show in this paper, I/O has become the limiting factor in scaling down size and power toward the goal of invisible computing. Achieving this goal will require composing optimized and specialized-yet reusable-components with an interconnect that permits tiny, ultra-low power systems. In contras...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:Proceedings - International Symposium on Computer Architecture Jg. 2015; S. 629 - 641
Hauptverfasser: Pannuto, Pat, Lee, Yoonmyung, Kuo, Ye-Sheng, Foo, ZhiYoong, Kempke, Benjamin, Kim, Gyouho, Dreslinski, Ronald G., Blaauw, David, Dutta, Prabal
Format: Tagungsbericht Journal Article
Sprache:Englisch
Veröffentlicht: United States IEEE 01.06.2015
Schlagworte:
Chirp
Circuit faults
Clocks
Low-power electronics
Resistors
Tuning
Wires
ISSN:1063-6897
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:As we show in this paper, I/O has become the limiting factor in scaling down size and power toward the goal of invisible computing. Achieving this goal will require composing optimized and specialized-yet reusable-components with an interconnect that permits tiny, ultra-low power systems. In contrast to today's interconnects which are limited by power-hungry pull-ups or high-overhead chip-select lines, our approach provides a superset of common bus features but at lower power, with fixed area and pin count, using fully synthesizable logic, and with surprisingly low protocol overhead.
Bibliographie:ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 23
ISSN:1063-6897
DOI:10.1145/2749469.2750376