MBus: An ultra-low power interconnect bus for next generation nanopower systems

As we show in this paper, I/O has become the limiting factor in scaling down size and power toward the goal of invisible computing. Achieving this goal will require composing optimized and specialized-yet reusable-components with an interconnect that permits tiny, ultra-low power systems. In contras...

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Vydané v:Proceedings - International Symposium on Computer Architecture Ročník 2015; s. 629 - 641
Hlavní autori: Pannuto, Pat, Lee, Yoonmyung, Kuo, Ye-Sheng, Foo, ZhiYoong, Kempke, Benjamin, Kim, Gyouho, Dreslinski, Ronald G., Blaauw, David, Dutta, Prabal
Médium: Konferenčný príspevok.. Journal Article
Jazyk:English
Vydavateľské údaje: United States IEEE 01.06.2015
Predmet:
Chirp
Circuit faults
Clocks
Low-power electronics
Resistors
Tuning
Wires
ISSN:1063-6897
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Popis
Shrnutí:As we show in this paper, I/O has become the limiting factor in scaling down size and power toward the goal of invisible computing. Achieving this goal will require composing optimized and specialized-yet reusable-components with an interconnect that permits tiny, ultra-low power systems. In contrast to today's interconnects which are limited by power-hungry pull-ups or high-overhead chip-select lines, our approach provides a superset of common bus features but at lower power, with fixed area and pin count, using fully synthesizable logic, and with surprisingly low protocol overhead.
Bibliografia:ObjectType-Article-1
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ISSN:1063-6897
DOI:10.1145/2749469.2750376