Low-power Implementation of an Encryption/Decryption System with Asynchronous Techniques

An asynchronous VLSI implementation of the International Data Encryption Algorithm (IDEA) is presented in this paper. In order to evaluate the asynchronous design a synchronous version of the algorithm was also designed. VHDL hardware description language was used in order to describe the algorithm....

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Vydané v:	VLSI Design Ročník 2002; číslo 1; s. 455 - 468
Hlavní autori:	Sklavos, Nikos, Papakonstantinou, Alexandros, Theoharis, Spyros, Koufopavlou, Odysseas
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	Hindawi Limiteds 2002
Predmet:	IDEA algorithm Asynchronous VLSI implementation Encryption decryption algorithm Cryptography
ISSN:	1065-514X, 1563-5171
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