Early partial evaluation in a JIT-compiled, retargetable instruction set simulator generated from a high-level architecture description

Modern processor design tools integrate in their workflows generators for instruction set simulators (Iss) from architecture descriptions. Whilst these generated simulators are useful for design evaluation and software development, they suffer from poor performance. We present an ultra-fast Jit-comp...

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Vydané v:2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) s. 1 - 6
Hlavní autori: Wagstaff, Harry, Gould, Miles, Franke, Björn, Topham, Nigel
Médium: Konferenčný príspevok..
Jazyk:English
Vydavateľské údaje: New York, NY, USA ACM 29.05.2013
IEEE
Edícia:ACM Conferences
Predmet:
Benchmark testing
Computer architecture
Computer systems organization > Architectures > Parallel architectures > Very long instruction word
Computer systems organization > Architectures > Serial architectures > Complex instruction set computing
Computer systems organization > Architectures > Serial architectures > Reduced instruction set computing
Computer systems organization > Dependable and fault-tolerant systems and networks
Decoding
General and reference > Cross-computing tools and techniques > Performance
Generators
Heuristic algorithms
Networks > Network performance evaluation
Optimization
Software and its engineering > Software notations and tools > Compilers
ISBN:1450320716, 9781450320719
ISSN:0738-100X
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Popis
Shrnutí:Modern processor design tools integrate in their workflows generators for instruction set simulators (Iss) from architecture descriptions. Whilst these generated simulators are useful for design evaluation and software development, they suffer from poor performance. We present an ultra-fast Jit-compiled Iss generated from an ArchC description. We also introduce a novel partial evaluation optimisation, which further improves Jit compilation time and code quality. This results in a simulation rate of 510Mips for an Arm target across 45 Eembc and Spec benchmarks. On average, our Iss is 1.7 times faster than Simit-Arm, one of the fastest Iss generated from an architecture description.
ISBN:1450320716
9781450320719
ISSN:0738-100X
DOI:10.1145/2463209.2488760