A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs

This paper presents a digital VLSI design flow to create secure, side-channel attack (SCA) resistant integrated circuits. The design flow starts from a normal design in a hardware description language such as VHDL or Verilog and provides a direct path to a SCA resistant layout. Instead of a full cus...

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Vydané v:	Design, Automation and Test in Europe s. 58 - 63
Hlavní autori:	Tiri, Kris, Verbauwhede, Ingrid
Médium:	Konferenčný príspevok..
Jazyk:	English
Vydavateľské údaje:	Washington, DC, USA IEEE Computer Society 01.01.2005 IEEE
Edícia:	ACM Conferences
Predmet:	Algorithm design and analysis Circuit simulation CMOS process Digital integrated circuits Hardware > Hardware validation Hardware > Very large scale integration design Hardware design languages Libraries Measurement standards Process design Security and privacy > Cryptography > Cryptanalysis and other attacks Security and privacy > Cryptography > Public key (asymmetric) techniques Security and privacy > Cryptography > Public key (asymmetric) techniques > Public key encryption Security and privacy > Intrusion/anomaly detection and malware mitigation Social and professional topics > Computing > technology policy > Computer crime Very large scale integration
ISBN:	9780769522883, 0769522882
ISSN:	1530-1591
On-line prístup:	Získať plný text
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