A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs

This paper presents a digital VLSI design flow to create secure, side-channel attack (SCA) resistant integrated circuits. The design flow starts from a normal design in a hardware description language such as VHDL or Verilog and provides a direct path to a SCA resistant layout. Instead of a full cus...

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Veröffentlicht in:Design, Automation and Test in Europe S. 58 - 63
Hauptverfasser: Tiri, Kris, Verbauwhede, Ingrid
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: Washington, DC, USA IEEE Computer Society 01.01.2005
IEEE
Schriftenreihe:ACM Conferences
Schlagworte:
Algorithm design and analysis
Circuit simulation
CMOS process
Digital integrated circuits
Hardware > Hardware validation
Hardware > Very large scale integration design
Hardware design languages
Libraries
Measurement standards
Process design
Security and privacy > Cryptography > Cryptanalysis and other attacks
Security and privacy > Cryptography > Public key (asymmetric) techniques
Security and privacy > Cryptography > Public key (asymmetric) techniques > Public key encryption
Security and privacy > Intrusion/anomaly detection and malware mitigation
Social and professional topics > Computing > technology policy > Computer crime
Very large scale integration
ISBN:9780769522883, 0769522882
ISSN:1530-1591
Online-Zugang:Volltext
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Zusammenfassung:This paper presents a digital VLSI design flow to create secure, side-channel attack (SCA) resistant integrated circuits. The design flow starts from a normal design in a hardware description language such as VHDL or Verilog and provides a direct path to a SCA resistant layout. Instead of a full custom layout or an iterative design process with extensive simulations, a few key modifications are incorporated in a regular synchronous CMOS standard cell design flow. We discuss the basis for side-channel attack resistance and adjust the library databases and constraints files of the synthesis and place & route procedures accordingly. Experimental results show that a DPA attack on a regular single ended CMOS standard cell implementation of a module of the DES algorithm discloses the secret key after 200 measurements. The same attack on a secure version still does not disclose the secret key after more than 2000 measurements.
Bibliographie:SourceType-Conference Papers & Proceedings-1
ObjectType-Conference Paper-1
content type line 25
ISBN:9780769522883
0769522882
ISSN:1530-1591
DOI:10.1109/DATE.2005.44